arXiv subjects

Anibal Pacheco-Sanchez

Publications and source records attributed to Anibal Pacheco-Sanchez.

At least 19 recordsLinked to original sources

arXiv2025

An extended low-frequency noise compact model for single-layer graphene FETs including correlated mobility fluctuations effect

Correlated mobility fluctuations are considered in the physics-based carrier number fluctuation deltaN low-frequency noise (LFN) compact model of single-layer graphene field effect transistors (GFET) in the present study. Trapped charge density and Coulomb scattering coefficient deltaN LFN parameters are obtained after applying a parameter extraction methodology, adapted from conventional silicon technologies, to the linear ambipolar regions of GFETs. Appropriate adjustments are considered in the method according to GFETs physical characteristics. Afterwards, Hooge mobility as well as series resistance fluctuations LFN parameters can be extracted. The updated LFN model is validated with experimental data from various long and short-channel GFETs at an extended range of gate and drain bias conditions.

cond-mat.mes-hall↗

arXiv2025

A Taylor Series Approximation Model for Characterizing the Output Resistance of a GFET

The mobility-degradation-based model for the drain-to-source or output resistance of a graphene field-effect-transistor is linearized here using a Taylor series approximation. This simplification is shown to be valid from magnitudes of the gate voltage not significantly higher than the Dirac voltage, and it enables the analytical determination of the transconductance parameter, the voltage related to residual charges, and a bias-independent series resistance of the GFET. Furthermore, a continuous representation of the device's static response is achieved when substituting the extracted parameters into the model, regardless the transfer characteristic symmetry with respect to the Dirac voltage.

cond-mat.mes-hall↗

arXiv2024

A Scalable Compact Model for the Static Drain Current of Graphene FETs

The main target of this article is to propose for the first time a physics-based continuous and symmetric compact model that accurately captures IV experimental dependencies induced by geometrical scaling effects for graphene transistor (GFET) technologies. Such a scalable model is an indispensable ingredient for the boost of large-scale GFET applications, as it has been already proved in solid industry-based CMOS technologies. Dependencies of the physical model parameters on channel dimensions, are thoroughly investigated, and semi?empirical expressions are derived, which precisely characterize such behaviors for an industry-based GFET technology, as well as for others developed in research labs. This work aims at the establishment of the first industry standard GFET compact model that can be integrated in circuit simulation tools and hence, can contribute to the update of GFET technology from the research level to massive industry production.

physics.app-ph↗

arXiv2023

Exploiting ambipolarity in graphene field-effect transistors for novel designs on high-frequency analog electronics

Exploiting ambipolar electrical conductivity based on graphene field-effect transistors has raised enormous interest for high-frequency (HF) analog electronics. Controlling the device polarity, by biasing the graphene transistor around the vertex of the V-shaped transfer curve, enables to redesign and highly simplify conventional analog circuits, and simultaneously to seek for multifunctionalities specially in the HF domain. We present, here, new insights for the design of different HF applications such as power amplifiers, mixers, frequency multipliers, phase shifters, and modulators that specifically leverage the inherent ambipolarity of graphene-based transistors.

cond-mat.mes-hall↗

arXiv2023

Characterization of the Intrinsic and Extrinsic Resistances of a Microwave Graphene FET Under Zero Transconductance Conditions

Graphene field-effect transistors exhibit negligible transconductance under two scenarios: for any gate-to-source voltage when the drain-to-source voltage is set to zero, and for an arbitrary drain-to-source voltage provided that the gate-to-source voltage equals the Dirac voltage. Hence, extracting the channel and the parasitic series resistances from S-parameters under these conditions enables analyzing their dependence on the gate and drain biases. This is fundamental to assess the portion of the output resistance that is controlled by the gate. Besides, the drain bias dependence of the drain and source resistances is also evidenced. Within the proposal, resistive components accounting for the lossy nature of the gate capacitance are incorporated into the model, which exhibits a broadband correlation with experimental data. This avoids the series resistances to be considered as frequency dependent in the model.

cond-mat.mes-hall↗

arXiv2023

Static and small-signal modeling of radiofrequency hexagonal boron nitride switches

A first modeling approximation of the general performance of radiofrequency (RF) switches based on hexagonal boron nitride (hBN), a two-dimensional (2D) dielectric material is presented. The I-V characteristics intrinsic and extrinsic impedance parameters, the return loss, insertion loss and isolation of RF 2D switches fabricated with hBN are described here by a equivalent circuit models. Straightforward analytical expressions are obtained. In contrast to conventional switches, the unique RF performance of the hBN switch, at ON-state, i.e., a direct improvement with frequency of the insertion loss, is accurately described by considering a capacitor in the intrinsic part of the model. The latter is suggested to be related to storaged charge during the resistive switching mechanism. The highest mean relative error obtained between modeling and measurements of the return loss is of 7.6% with the approach presented here which overcomes the 42.5% of difference obtained with a previous model with an incomplete intrinsic device description.

physics.app-ph↗

arXiv2023

Physics-based bias-dependent compact modeling of 1/f noise in single- to few- layer 2D-FETs

1/f noise is a critical figure of merit for the performance of transistors and circuits. For two-dimensional devices (2D-FETs), and especially for applications in the GHz range where short-channel FETs are required, velocity saturation (VS) effect can result in the reduction of 1/f noise at high longitudinal electric fields. A new physics-based compact model is for the first time introduced for single- to few- layer 2D-FETs in this study, precisely validating 1/f noise experiments for various types of devices. The proposed model mainly accounts for the measured 1/f noise bias dependence as the latter is defined by different physical mechanisms. Thus, analytical expressions are derived, valid in all regions of operation in contrast to conventional approaches available in literature so far, accounting for carrier number fluctuation (DN), mobility fluctuation (Dmu}) and contact resistance (DR) effects based on the underlying physics that rules these devices. DN mechanism due to trapping/detrapping together with an intense Coulomb scattering effect, dominates 1/f noise from medium to strong accumulation region while Dmu, is also demonstrated to modestly contribute in subthreshold region. DR can also be significant in very high carrier density. The VS induced reduction of 1/f noise measurements at high electric fields, is also remarkably captured by the model. The physical validity of the model can also assist in extracting credible conclusions when conducting comparisons between experimental data from devices with different materials or dielectrics.

cond-mat.mes-hall↗

arXiv2023

Straightforward Bias and Frequency Dependent Small-Signal Model Extraction for Single-Layer Graphene FETs

We propose an explicit small-signal graphene field-effect transistor (GFET) parameter extraction procedure based on a charge-based quasi-static model. The dependence of the small-signal parameters on both gate voltage and frequency is precisely validated by high-frequency (up to 18 GHz) on-wafer measurements from a 300 nm device. These parameters are studied simultaneously, in contrast to other works which focus exclusively on few. Efficient procedures have been applied to GFETs for the first time to remove contact and gate resistances from the Y-parameters. The use of these methods yields straightforward equations for extracting the small-signal model parameters, which is extremely useful for radio-frequency circuit design. Furthermore, we show for the first time experimental validation vs. both gate voltage and frequency of the intrinsic GFET non-reciprocal capacitance model. Accurate models are also presented for the gate voltage-dependence of the measured unity-gain and maximum oscillation frequencies as well as of the current and power gains.

cond-mat.mes-hall↗

arXiv2023

Gate Tunable Lateral 2D pn Junctions: An Analytical Study of Its Electrostatics

The electrostatics of two-dimensional (2D) lateral pn homojunctions considering the impact of electrostatic doping by means of two split bottom-gates are studied here. Analytical expressions are obtained from the solution of the 2D Poisson equation considering a depletion approximation. Straightforward analytical models for the electrostatic potential and the depletion width within both the dielectric and the 2D semiconductor are obtained for both the symmetrical and asymmetrical cases. In contrast to the case of devices with chemical doping, the obtained depletion width model of devices with electrostatic doping do not depend on the dielectric constant but only on the electrostatic potential and oxide thickness. The models describe the electrostatics of gate-tunable 2D pn junctions at arbitrary bias. A benchmark against numerical device simulations of MoS2-based pn junctions validate the analytical models.

cond-mat.mes-hall↗

arXiv2022

Schottky-like barrier characterization of field-effect transistors with multiple quasi-ballistic channels

The potential barrier height at the interface formed by a metal contact and multiple one-dimensional (1D) quasi-ballistic channels in field-effect transistors (FETs) is evaluated across different carbon nanotube and nanowire device technologies by means of a Landauer-Büttiker-based extraction methodology (LBM) adapted for multiple 1D-channels. The extraction methodology yields values for an effective Schottky barrier height and a gate coupling coefficient, an indicator of the device working at the quantum capacitance limit. The novel LBM-based approach embracing the mechanisms in 1D electronics is compared to the conventional activation energy method not considering such effects. The latter approach underestimates the potential barrier height at metal-channel interfaces in comparison to the novel methodology. A test structure based on a displaced gate device is proposed based on numerical device simulation results towards an improved accuracy of the method.

cond-mat.mes-hall↗

arXiv2022

An extraction method for mobility degradation and contact resistance of graphene transistors

The intrinsic mobility degradation coefficient, contact resistance and the transconductance parameter of graphene field-effect transistors (GFETs) are extracted for different technologies by considering a novel transport model embracing mobility degradation effects within the charge channel control description. By considering the mobility degradation-based model, a straightforward extraction methodology, not provided before, is enabled by applying the concept of the well-known Y-function to the \textit{I-V} device characteristics. The method works regardless the gate device architecture. An accurate description of experimental data of fabricated devices is achieved with the underlying transport equation by using the extracted parameters. An evaluation of the channel resistance, enabled by the extracted parameters here, has been also provided.

cond-mat.mes-hall↗

arXiv2021

Bias-dependent intrinsic RF thermal noise modeling and characterization of single layer graphene FETs

In this article, the bias-dependence of intrinsic channel thermal noise of single-layer graphene field-effect transistors (GFETs) is thoroughly investigated by experimental observations and compact modeling. The findings indicate an increase of the specific noise as drain current increases whereas a saturation trend is observed at very high carrier density regime. Besides, short-channel effects like velocity saturation also result in an increment of noise at higher electric fields. The main goal of this work is to propose a physics-based compact model that accounts for and accurately predicts the above experimental observations in short-channel GFETs. In contrast to long-channel MOSFET based models adopted previously to describe thermal noise in graphene devices without considering the degenerate nature of graphene, in this work a model for short-channel GFETs embracing the 2D materials underlying physics and including a bias dependency is presented. The implemented model is validated with de-embedded high frequency data from two short-channel devices at Quasi-Static region of operation. The model precisely describes the experimental data for a wide range of low to high drain current values without the need of any fitting parameter. Moreover, the consideration of the degenerate nature of graphene reveals a significant decrease of noise in comparison with the non degenerate case and the model accurately captures this behavior. This work can also be of outmost significance from circuit designers aspect, since noise excess factor, a very important figure of merit for RF circuits implementation, is defined and characterized for the first time in graphene transistors.

cond-mat.mes-hall↗

arXiv2021

A small-signal description of black phosphorus transistor technologies for high-frequency applications

This work presents a small-signal high-frequency (HF) equivalent circuit (EC) to model AC performances of black-phosphorous field-effect transistors (BPFETs). The proposed EC is able to describe correctly both the experimental HF intrinsic and extrinsic figures of merit, as well as S-parameters, from different BPFET technologies. Single- and double-stage radio frequency gain amplifiers, are designed at 2.4 GHz using the experimentally-calibrated small-signal BPFET EC. Results show high-gain high-selective BPFET-based amplifiers.

physics.app-ph↗

arXiv2021

Multifunctional high-frequency circuit capabilities of ambipolar carbon nanotube FETs

An experimentally-calibrated carbon nanotube compact transistor model has been used here to design two high-frequency (HF) circuits with two different functionalities each: a phase configurable amplifier (PCA) and a frequency configurable amplifier (FCA). The former design involves an in-phase amplifier and an inverting amplifier while the latter design embraces a frequency doubler as well as a distinct inverting amplifier. The specific functionality selection of each of the two HF circuit designs is enabled mainly by the inherent ambipolar feature at a device level. Furthermore, at a circuit level the matching networks are the same regardless the operation mode. In-phase and inverting amplification are enabled in the PCA by switching the gate-to-source voltage (VGS) from -0.3 V to 0.9 V while the drain-to-source voltage (VDS) remains at 3 V. By designing carefully the matching and stability networks, power gains of 4.5 dB and 6.7 dB at 2.4 GHz for the in-phase and inverting operation mode have been achieved, respectively. The FCA, in its frequency doubler operation mode, exhibits 20 dBc of fundamental-harmonic suppression at 2.4 GHz when an input signal at 1.2 GHz is considered. This frequency doubler functionality is enabled at VGS=0.3 V, whereas at VGS=0.9 V amplification of 4.5 dB is obtained while VDS remains at 3 V in both cases. In both configurable circuits the stabilization and matching networks are the same regardless the bias-chosen operation mode. The circuits performance degradation due to metallic tubes in the device channel is studied as well as the impact of non-ideal inductors in each design. PCA and FCA operation modes are further exploited in high-frequency modulators.

physics.app-ph↗

arXiv2021

Unveiling the impact of the bias-dependent charge neutrality point on graphene-based multi-transistor applications

The Dirac voltage of a graphene field-effect transistor (GFET) stands for the gate bias that sets the charge neutrality condition in the channel, thus resulting in a minimum conductivity. Controlling its dependence on the terminal biases is crucial for the design and optimization of radio-frequency applications based on multiple GFETs. However, the previous analysis of such dependence carried out for a single device can lead to confusion and if not properly understood could result in circuit designs with poor performance. The control of the Dirac point shift (DPS) is particularly important for the deployment of graphene-based differential circuit topologies where keeping a strict symmetry between the electrical balanced branches is crucial for exploiting the advantages of such topologies. This note sheds light on the impact of terminal biases on the DPS in a real device and sets a rigorous methodology to control it so to eventually optimize and exploit the performance of radio-frequency applications based on GFETs.

physics.app-ph↗

arXiv2020

A small-signal GFET equivalent circuit considering an explicit contribution of contact resistances

A small-signal equivalent circuit for graphene field-effect transistors is proposed considering the explicit contribution of effects at the metal-graphene interfaces by means of contact resistances. A methodology to separate the contact resistances from intrinsic parameters, obtained by a de-embedding process, and extrinsic parameters of the circuit is considered. The experimental high-frequency performance of three devices from two different GFET technologies is properly described by the proposed small-signal circuit. Some model parameters scale with the device footprint. The correct detachment of contact resistances from the internal transistor enables to assess their impact on the intrinsic cutoff frequency of the studied devices.

physics.app-ph↗

arXiv2020

Experimental observation and modeling of the impact of traps on static and analog/HF performance of graphene transistors

The trap-induced hysteresis on the performance of a graphene field-effect transistor is experimentally diminished here by applying consecutive gate-to-source voltage pulses of opposing polarity. This measurement scheme is a practical and suitable approach to obtain reproducible device characteristics. Trap-affected and trap-free experimental data enable a discussion regarding the impact of traps on static and dynamic device performance. An analytical drain current model calibrated with the experimental data enables the study of the traps effects on the channel potential within the device. High-frequency figures of merit and the intrinsic gain of the device obtained from both experimental and synthetic data with and without hysteresis show the importance of considering the generally overlooked impact of traps for analog and high-frequency applications.

cond-mat.mes-hall↗

arXiv2020

Contact resistance assessment and high-frequency performance projection of black phosphorus field-effect transistor technologies

In this work, an evaluation of the contact quality of black phosphorus (BP) field-effect transistors (FETs) from different technologies previously reported is performed by means of an efficient and reliable contact resistance extraction methodology based on individual device practical characteristics. A good agreement is achieved between the extracted values with the Y-function method used here and reference values obtained with other methods considering internal values as well as with more expensive methods involving fabricated test structures. The method enables a direct evaluation of different steps in the same technology and it embraces the temperature dependence of the contact characteristics. Channel phenomena have no impact on the extracted contact resistance values. High-frequency performance projections are obtained for fabricated devices based on the extracted contact resistance.

cond-mat.mes-hall↗