arXiv subjects

Asif Khan

Publications and source records attributed to Asif Khan.

At least 19 recordsLinked to original sources

arXiv2026

Complete Au-free Metallization Platform for UWBG Al$_{0.65}$Ga$_{0.35}$N channel MOS-HEMTs using Ti/Al/Ti Ohmic Contacts and Refractory TiN/Pt Gates

Au-free ohmic contacts and refractory gate stacks are critical for integrating ultra-wide-bandgap (UWBG) Al-rich AlGaN transistors with Si-CMOS technology. In this work, we demonstrate, to our knowledge, the first complete Au-free metallization platform for Al$_{0.65}$Ga$_{0.35}$N-channel MOS-HEMTs, combining electron-beam-evaporated and sputtered Ti/Al/Ti ohmic contacts with sputtered TiN and Pt gate metals. The Ti/Al/Ti contacts achieved a contact resistance of approximately 7.5--7.7 $Ω\cdot$mm while being fully Au-free. This contact resistance is achieved using a 600 $^\circ$C anneal, substantially below the 850--950 $^\circ$C typically required for Au-capped Ti/Al/X/Au contacts on Al-rich AlGaN, indicating a reduced thermal budget and improved compatibility with silicon-CMOS foundries. TiN gates deliver drain-current density up to 450 mA/mm at $V_{\mathrm{th}} = -13$ V, whereas Pt gates shift $V_{\mathrm{th}}$ to -2.5 V with a reduced current drive of 220 mA/mm, reflecting the effects of gate work function. TiN-gated devices exhibit lower current degradation under pulsed operation and a higher critical breakdown field ($E_{\mathrm{c}} \approx 3.5$ MV/cm) than Pt-gated devices ($E_{\mathrm{c}} \approx 2.98$ MV/cm), measured without field plating at $L_{\mathrm{GD}} = 2.3$ $μ$m. Collectively, these results establish a low-thermal-budget, fully Au-free, CMOS-compatible metallization platform for high-performance Al-rich AlGaN UWBG power electronics.

physics.app-ph↗

arXiv2026

800 $^\circ$C Air-Ambient Operation of Extreme-Bandgap Al$_{x}$Ga$_{1-x}$N (x>0.6) Digital and Random-Alloy Channel HEMTs

This work demonstrates the high-temperature (room to 800 $^\circ$C) operation of thin Al$_{0.62}$Ga$_{0.38}$N digital alloy (DA) short-period superlattice (SPSL), and random alloy (RA) Al$_{0.64}$Ga$_{0.36}$N channel MOSHEMTs on sapphire. The RA devices employ a doped $n^{+}$-85%-Al barrier and a highly doped $n^{++}$-Al$_{0.86\rightarrow0.20}$Ga$_{0.14\rightarrow0.80}$N reverse-graded layer (RGL) for surface ohmic contact formation, whereas the DA devices employ a binary AlN barrier and selectively regrown $n^{++}$-GaN source/drain contacts. At 800 $^\circ$C, the DA channel devices exhibit better thermal stability: their saturated drain current decreases from 460 to 172 mA/mm (62.6%) compared with 338 to 98 mA/mm (71.0%) for the RA channel, and a lower subthreshold swing (459 for DA versus 550 mV/dec for RA). All tested DA devices also exhibit superior threshold-voltage stability ($<\pm 10\%$ versus $>\pm 19\%$ for RA) and maintain an ON/OFF current ratio >$10^4$ at 800 $^\circ$C, compared with ~$10^3$ for RA, thus establishing the DA channel HEMTs as a promising new platform for high-temperature electronics.

physics.app-ph↗

arXiv2026

Dynamic Planar Graph Isomorphism is in DynFO

Consider two planar graphs which are subject to edge insertions and deletions. We show that whether the two graphs are isomorphic can be maintained with first-order logic formulas and auxiliary data of polynomial size. This places the dynamic planar graph isomorphism problem into the dynamic descriptive complexity class DynFO. As a consequence, there is a dynamic constant-time parallel algorithm with polynomial-size auxiliary data which maintains whether two dynamic planar graphs are isomorphic.

cs.LO↗

arXiv2026

Direct Observation of Nanoscale Polarization Switching in HZO Ferroelectrics Using STEM-EBIC

We report the experimental observation of discrete ferroelectric switching down to 0.475 nm x 0.475 nm in HfO2-based ferroelectrics using correlated STEM electron beam induced current (EBIC) imaging and nanoscale voltage pulsing. These high-resolution measurements reveal single-domain switching events characterized by abrupt, bi-state transitions with no intermediate polarization states. By mapping polarization-voltage behavior and switching kinetics across thousands of domains, we extract spatially resolved switching thresholds (Emin), switching speeds (tsw), and remanent polarization (2Pr), uncovering robust scaling trends. Larger domains exhibit nearly twice the polarization and faster switching despite higher Emin, while smaller domains switch more slowly at the same field. Sub-domain imaging enables quantification of variation scaling: polarization variation increases linearly logarithmically with area, with inter-domain variation dominating intra-domain variation. Importantly, we show that multi-bit operation arises from the statistical distribution of domain-level switching, rather than partial polarization, enabling distinct and reliable states in devices as small as 0.01 um2. These findings provide a foundational experimental framework for designing scalable, multi-bit ferroelectric memory based on grain- and domain-level heterogeneity.

cond-mat.mes-hall↗

arXiv2026

Multi-bit Ferroelectric-NAND for High-throughput Massive Database Search

The growing demand for large-scale database search in data-intensive applications, ranging from proteomics to autonomous systems, has exposed fundamental limitations in von Neumann architectures due to memory bandwidth and energy constraints. Hyperdimensional (HD) computing offers a robust and parallelizable framework for such tasks, but its practical implementation remains challenged by high memory demands. Ultra-high-density, energy-efficient ferroelectric NAND (FE-NAND) memory provides a potential solution by enabling in-situ computation. We fabricate quad-level FE-NAND strings with wide memory windows, disturb resilience, and robust retention. Using these planar FE-NAND strings as building blocks, we experimentally demonstrate in-situ multi-level cell (MLC) dot product operations at the single-cell level and, using experimentally calibrated physics-based simulations, demonstrate Hamming similarity calculations between reference and query hypervectors (HV). This platform leverages the inherent error tolerance of HD computing to achieve >90% search accuracy even at high logic levels (TLC, QLC). When benchmarked on Open Modification Search (OMS) tasks in proteomics with TB-scale datasets, our system shows nearly 1,000x speedup and over 10,000x energy efficiency improvement compared to incumbent solutions. These results establish FE-NAND as a viable in-storage compute architecture for large-scale, high-dimensional data processing.

cond-mat.mes-hall↗

arXiv2026

Experiments and Modeling of Defect Dynamics and BTI Behavior in Doped InO TFTs during $400^\circ$C Post-Processing Forming Gas Annealing

We investigate the impact of a monolithic three-dimensional (M3D) integration process-critical $400^\circ$C post-processing forming gas anneal (FGA) on the electrical performance, reliability, and defect evolution of oxide-channel thin-film transistors (TFTs), combining systematic experiments with density-functional-theory (DFT)-based liquid-quench molecular-dynamics (MD) simulations. Indium tungsten oxide (IWO) TFTs are employed as a model system and encapsulated with a thin 3 nm Al$_2$O$_3$ / 3 nm HfO$_2$ hybrid layer that effectively suppresses external hydrogen ingress. We reveal a non-monotonic evolution of device behavior during FGA, governed by initial densification followed by partial crystallization. Short-duration FGA (10 min) induces channel densification and the formation of shallow, delocalized defect states, leading to pronounced positive bias temperature instability (PBTI) degradation and the emergence of a characteristic transfer-curve "kink." With prolonged annealing (>40 min), partial crystallization of the oxide channel occurs, stabilizing hydrogen in deep, localized defect states, suppressing hydrogen mobility, and restoring device reliability. As a result, the PBTI shift is reduced to 10.4 mV after 2000 seconds of stress, accompanied by complete elimination of the transfer-curve kink. These findings provide a mechanistic understanding of hydrogen-defect interactions during high-temperature post-processing FGA and demonstrate that appropriate hydrogen-blocking encapsulation enables oxide-channel TFT integration without compromising electrical performance or reliability.

cond-mat.mtrl-sci↗

arXiv2026

Agentic TCAD Calibration Workflow for Oxide Semiconductor Transistors

Experimental TCAD calibration is essential for predictive technology modeling of emerging oxide semiconductor transistors. However, it remains time-consuming and expert dependent because of model ambiguity. Multiple physical models and parameter sets can reproduce the same measured transfer characteristics, while local fitting alone cannot uniquely identify the underlying device physics. We present the first demonstration of an agentic TCAD calibration workflow for a fabricated bottom-gate In--W--O (BG-IWO) transistor. Starting from the measured transfer curve and device information, the workflow uses measurement--TCAD residuals and local sensitivity tests to select bounded parameter corrections or evaluate additional physical models, and accept only updates that improve device metrics. The LLM agent orchestrates the workflow, while Sentaurus governs the device physics. For the 2\%-W reference device, five agent-suggested updates yield a fixed calibrated model, reducing the multi-metric device objective $J$ by 14.3$\times$. Maximum $V_{\mathrm{th}}$/$I_{\mathrm{on}}$ errors are 36.1~mV/0.022 decade for varying-drain-bias tests and 46.2~mV/0.062 decade for varying-channel-length tests, demonstrating model transferability across bias and geometry rather than a local parameter fit. W-composition tests provide process-sensitive insight. This agentic workflow provides a faster route to model development for emerging device technologies.

physics.ins-det↗

arXiv2026

Neural Network Operator-Based Fractal Approximation: Smoothness Preservation and Convergence Analysis

This paper introduces the construction of fractal interpolation functions (FIFs), whose graphs are the attractors of an iterated function system (IFS). Integrating concepts from approximation theory, $α$-fractal functions are constructed, employing shallow neural network operators. Based on the same methodology, we developed fractal interpolation functions using only discrete function values, unlike traditional methods that require each value of the target function. In order to preserve the smoothness of the target function, a method for constructing such FIFs is introduced, employing four-layered neural network operators, i.e., whenever $f \in C^{r}[a,b]$, the corresponding FIF $f^α \in C^{r}[a,b]$. This work uses key approximation theory tools, such as the modulus of continuity and interpolation operators, to develop convergence results and uniform approximation error bounds. To validate the theoretical results obtained, numerical experiments with graphical analysis using Python is provided.

cs.LG↗

arXiv2026

Connectivity Augmentation of Plane Graphs

We study the problem of connectivity augmentation of a planar graph, while preserving planarity. This problem is motivated by many real-world settings such as road-networks, power-networks etc. In these settings, it is crucial to preserve the original planar embedding after augmentation. In 2009, Gutwenger and Mutzel gave a constructive algorithm showing that a connected planar graph with a fixed embedding (a plane graph) can be optimally augmented to a biconnected graph without crossings while preserving the embedding. We further this line of research, by giving an algorithm that computes a minimum set of edges that makes a connected plane graph 2-edge-connected in $O(|V|(1+α(|V|)))$ time and linear space, where $α$ is the inverse Ackermann function.

cs.DS↗

arXiv2026

Capacity and Redundancy Trade-offs in Multi-Task Learning

In multi-task learning (MTL) negative transfer is often considered as an optimization artifact, but it can also be viewed as a consequence of limited shared capacity and weak task redundancy. We investigate this effect through a Capacity--Redundancy (CR) identity that decomposes the sum of per-task predictive informations into joint predictive information that includes label redundancy defined via total correlation (TC), and a residual coupling term that quantifies interference left unresolved by the shared representation. Additionally, we show two key results: (i) a clustering-gap decomposition that gives a necessary and sufficient condition for clustered sharing to outperform global sharing, and (ii) a gradient--TC bridge in a Gaussian multi-task model that formally justifies gradient cosine similarity as a proxy for redundancy ordering. Empirically, we estimate the residual coupling $Δ$ from validation residual correlations, showing that clustered LoRA substantially reduces $\widehatΔ$, outperforms size-matched random partitions, and results in statistically significant gains with multi-seed confidence intervals.

cs.LG↗

arXiv2026

Thermal Processing Limits in Oxide-Channel Ferroelectric Field Effect Transistors

In this work, we report a systematic study of the impact of high-temperature post-capping thermal annealing on the memory characteristics of Oxide-semiconductor channel ferroelectric field-effect transistors (OS-FeFETs). Using an identical engineered ferroelectric gate stack 8nm Hf0.5Zr0.5O2 (HZO) / 3 nm Al2O3 / 8 nm HZO (8/3/8) and a hybrid capping layer (3 nm HfO2 + 3 nm Al2O3), 10 percent Ga doped InO (IGO) channel and 4 percent W doped InO (IWO) channel FeFETs remain functional after annealing at temperatures up to 650 C for durations of up to 30 min and 10 min, respectively; further annealing results in irreversible loss of conduction and device failure. Detailed electrical analysis reveals that the MW enhancement originates from a preferential positive shift in the erased-state threshold voltage, while the programmed-state threshold voltage remains comparatively stable. Grazing-incidence X-ray diffraction measurements further indicate structural evolution in the IWO and IGO oxide channels with increasing annealing temperature, supporting the observed electrical trends.

cond-mat.mtrl-sci↗

arXiv2026

A Promising Ohmic Contacts Approach for High-Al AlxGa1-xN (x>0.6) Channel HEMTs with AlN/GaN Digital Alloy Channel

In this paper we report a novel ohmic contact formation scheme for Extreme Bandgap (EBG) AlxGa1-xN (x>0.6) channel HEMTs with undoped barrier layers. Our approach consists of using a new low temperature (LT) pulsed metal-organic chemical vapor deposition (PMOCVD) doping scheme for the n++-GaN regrown contacts and an AlxGa1-xN digital alloy (DA) channel layer comprising short period super lattices (SPSL) of AlN and GaN. Pulsed growth and doping yield a sheet resistivity which is a factor of 3-5 lower than that of conventional doped n++-GaN layers grown under identical conditions. Moreover, the regrown n++-GaN layer has no hetero-barrier with the GaN layers of the AlxGa1-xN DA channel. These innovations led to MOCVD regrown linear ohmic contacts and a record-low contact resistance Rc ~6.5 Ω-mm to the Al0.62Ga0.38N DA channel layer of a HEMT with AlN barrier layer.

physics.app-ph↗

arXiv2026

Physics-informed AI Accelerated Retention Analysis of Ferroelectric Vertical NAND: From Day-Scale TCAD to Second-Scale Surrogate Model

Ferroelectric field-effect transistors (FeFET)-based vertical NAND (Fe-VNAND) has emerged as a promising candidate to overcome z-scaling limitations with lower programming voltages. However, the data retention of 3D Fe-VNAND is hindered by the complex interaction between charge detrapping and ferroelectric depolarization. Developing optimized device designs requires exploring an extensive parameter space, but the high computational cost of conventional Technology Computer-Aided Design (TCAD) tools makes such wide-scale optimization impractical. To overcome these simulation barriers, we present a Physics-Informed Neural Operator (PINO)-based AI surrogate model designed for high-efficiency prediction of threshold voltage (Vth) shifts and retention behavior. By embedding fundamental physical principles into the learning architecture, our PINO framework achieves a speedup exceeding 10000x compared to TCAD while maintaining physical accuracy. The resulting surrogate provides a physics-consistent data engine for compact model parameter extraction and look-up-table (LUT) generation, directly supporting reliability-aware SPICE simulation of Fe-VNAND. This study demonstrates the model's effectiveness on a single FeFET configuration, serving as a pathway toward modeling the retention loss mechanisms.

cs.LG↗

arXiv2026

Engineering Wake-Up-Free Ferroelectric Capacitors with Enhanced High-Temperature Reliability

We systematically explore the design space of ferroelectric hafnium-zirconium oxide (H0.5Z0.5O or HZO) heterostructures for reliable high temperature operation. HZO films are deposited using thermal and plasma-enhanced atomic layer deposition (Th-ALD and PE-ALD) on tungsten (W) and titanium nitride (TiN) bottom electrodes (BE), while maintaining identical top electrodes. We demonstrate that PE-ALD HZO capacitors integrated with W BE exhibit wake-up-free switching up to 125C, along with significantly improved endurance compared to Th-ALD HZO/W devices across a wide temperature range (85-125C). By decoupling the contributions of the plasma-deposited HZO film and the oxidized bottom interface inherently formed during PE-ALD, we identify the oxidized W interfacial layer (WOx) as the primary factor governing endurance enhancement and wake-up suppression at elevated temperatures, while the PE-ALD HZO film provides secondary benefits in reducing wake-up. In contrast, PE-ALD HZO capacitors fabricated on TiN BE show no substantial improvement in wake-up behavior or endurance relative to Th-ALD HZO/TiN devices, despite the formation of an unintentional TiOxNy interfacial layer, and instead exhibit degraded polarization. This difference arises from the significantly weaker endurance enhancement and no wake-up suppression provided by oxidized TiN compared to oxidized W under comparable oxidation conditions. Overall, PE-ALD HZO films enable superior ferroelectric performance at elevated temperatures only when deposited on W BE, while Th-ALD HZO films remain a viable option for high temperature operation on TiN BE. These findings clarify the interplay between deposition technique, electrode chemistry, and interfacial oxidation, and provide design guidelines for integrating ferroelectric memories into monolithic 3D systems under stringent thermal constraints.

cond-mat.mtrl-sci↗

arXiv2026

ALD Oxidant as A Tuning Knob for Memory Window Expansion in Ferroelectric FETs for Vertical NAND Applications

Dielectric inserts are widely used to expand the memory window (MW) in ferroelectric FETs (FeFETs) for vertical NAND applications, with prior efforts focused primarily on material selection and stack positioning. Here, we demonstrate that the ALD oxidant used for the Al2O3 interlayer serves as a process-level tuning knob for MW engineering. H2O-grown Al2O3 yields a significantly larger MW (7-8 V) compared to O3 (4 V) for both gate-injection (12/3) and tunnel dielectric (8/3/8) configurations. While the tunnel dielectric (8/3/8) stack maintains robust retention up to 1e4s at 125C despite the larger MW, the gate-injection (12/3) configuration exhibits pronounced retention degradation for the H2O case. The enhanced MW is attributed to higher interlayer leakage associated with H2O-based ALD. These results establish oxidant choice as a key process parameter for co-optimizing MW and retention in ferroelectric NAND technologies.

cond-mat.mtrl-sci↗

arXiv2026

Sub-nm2 ferroelectric domains via charged 180 degree walls in ZrO2

Flat phonon bands in fluorite ferroelectrics (HfO2 or ZrO2) shrink polar domains laterally to an irreducible half-unit-cell width (0.27 nm) within which the vertical arrangement of dipoles is expected to remain uniform. We report on the direct observation of nonuniform and nearly discrete vertical arrangements of dipoles in ZrO2 thin films consisting of closely spaced head-to-head (HH) and tail-to-tail (TT) charged 180 degree walls, each exhibiting a distinct bulk-like structure. These charged domain walls (CDWs) further compress the irreducibly narrow, laterally stacked domains vertically to a thickness of 1-2.75 nm, yielding in-plane domains with sub-nm2 footprints-among the smallest ever reported for any ferroelectric material. The HH and TT walls form due to their flat longitudinal optical (LO) polar bands and are electrostatically stabilized by bound-charge compensation via interstitial oxygen atoms, which act as natural structural defects at the HH walls. Moreover, these walls are predicted to be conducting and to exhibit ultralow propagation barriers, with HH walls (1.6 meV) being far more mobile than TT walls (22.3 meV), indicating strong potential for low-voltage, domain-wall-based nanoelectronics.

cond-mat.mtrl-sci↗

arXiv2026

ALD-Derived WO3-x Leads to Nearly Wake-Up-Free Ferroelectric Hf0.5Zr0.5O2 at Elevated Temperatures

Breaking the memory wall in advanced computing architectures will require complex 3D integration of emerging memory materials such as ferroelectrics-either within the back-end-of-line (BEOL) of CMOS front-end processes or through advanced 3D packaging technologies. Achieving this integration demands that memory materials exhibit high thermal resilience, with the capability to operate reliably at elevated temperatures such as 125C, due to the substantial heat generated by front-end transistors. However, silicon-compatible HfO2-based ferroelectrics tend to exhibit antiferroelectric-like behavior in this temperature range, accompanied by a more pronounced wake-up effect, posing significant challenges to their thermal reliability. Here, we report that by introducing a thin tungsten oxide (WO3-x) layer-known as an oxygen reservoir-and carefully tuning its oxygen content, ultra-thin Hf0.5Zr0.5O2 (5 nm) films can be made robust against the ferroelectric-to-antiferroelectric transition at elevated temperatures. This approach not only minimizes polarization loss in the pristine state but also effectively suppresses the wake-up effect, reducing the required wake-up cycles from 105 to only 10 at 125C- a qualifying temperature for back-end memory integrated with front-end logic, as defined by the JEDEC standard. First-principles density functional theory calculations reveal that WO3 enhances the stability of the ferroelectric orthorhombic phase at elevated temperatures by increasing the tetragonal-to-orthorhombic phase energy gap, and promoting favorable phonon mode evolution, thereby supporting o-phase formation under both thermodynamic and kinetic constraints.

cond-mat.mtrl-sci↗

arXiv2026

The First Switch Effect in Ferroelectric Field-Effect Transistors

In this work, a ferroelectric field-effect transistor (FEFET) is systematically characterized and compared with an equivalent standard MOSFET with an equivalent oxide thickness. We show that these two devices, with a silicon channel, exhibit similar pristine state transfer characteristics but starkly different endurance characteristics. In contrast to the MOSFET, the FEFET shows a significant increase in sub-threshold swing in the first write pulse. Based on this, we reveal that this first write pulse (cycle 1) generates more than half of the total traps generated during the fatigue cycling in FEFETs. We call this the 'First Switch Effect'. Further, by polarizing a pristine FEFET step by step, we demonstrate a direct correlation between the switched polarization and interface trap density during the first switch. Through charge pumping measurements, we also observe that continued cycling generates traps more towards the bulk of the stack, away from the Si/SiO2 interface in FEFETs. We establish that: (1) the first switch effect leads to approximately 50% of the total trap density (Nit) near the Si/SiO2 interface until memory window closure; and (2) further bipolar cycling leads to trap generation both at and away from Si/SiO2 interface in FEFETs.

cond-mat.mtrl-sci↗