arXiv subjects

Daewon Ha

Publications and source records attributed to Daewon Ha.

8 recordsLinked to original sources

arXiv2026

Thermal Processing Limits in Oxide-Channel Ferroelectric Field Effect Transistors

In this work, we report a systematic study of the impact of high-temperature post-capping thermal annealing on the memory characteristics of Oxide-semiconductor channel ferroelectric field-effect transistors (OS-FeFETs). Using an identical engineered ferroelectric gate stack 8nm Hf0.5Zr0.5O2 (HZO) / 3 nm Al2O3 / 8 nm HZO (8/3/8) and a hybrid capping layer (3 nm HfO2 + 3 nm Al2O3), 10 percent Ga doped InO (IGO) channel and 4 percent W doped InO (IWO) channel FeFETs remain functional after annealing at temperatures up to 650 C for durations of up to 30 min and 10 min, respectively; further annealing results in irreversible loss of conduction and device failure. Detailed electrical analysis reveals that the MW enhancement originates from a preferential positive shift in the erased-state threshold voltage, while the programmed-state threshold voltage remains comparatively stable. Grazing-incidence X-ray diffraction measurements further indicate structural evolution in the IWO and IGO oxide channels with increasing annealing temperature, supporting the observed electrical trends.

cond-mat.mtrl-sci↗

arXiv2026

ALD Oxidant as A Tuning Knob for Memory Window Expansion in Ferroelectric FETs for Vertical NAND Applications

Dielectric inserts are widely used to expand the memory window (MW) in ferroelectric FETs (FeFETs) for vertical NAND applications, with prior efforts focused primarily on material selection and stack positioning. Here, we demonstrate that the ALD oxidant used for the Al2O3 interlayer serves as a process-level tuning knob for MW engineering. H2O-grown Al2O3 yields a significantly larger MW (7-8 V) compared to O3 (4 V) for both gate-injection (12/3) and tunnel dielectric (8/3/8) configurations. While the tunnel dielectric (8/3/8) stack maintains robust retention up to 1e4s at 125C despite the larger MW, the gate-injection (12/3) configuration exhibits pronounced retention degradation for the H2O case. The enhanced MW is attributed to higher interlayer leakage associated with H2O-based ALD. These results establish oxidant choice as a key process parameter for co-optimizing MW and retention in ferroelectric NAND technologies.

cond-mat.mtrl-sci↗

arXiv2026

Physics-informed AI Accelerated Retention Analysis of Ferroelectric Vertical NAND: From Day-Scale TCAD to Second-Scale Surrogate Model

Ferroelectric field-effect transistors (FeFET)-based vertical NAND (Fe-VNAND) has emerged as a promising candidate to overcome z-scaling limitations with lower programming voltages. However, the data retention of 3D Fe-VNAND is hindered by the complex interaction between charge detrapping and ferroelectric depolarization. Developing optimized device designs requires exploring an extensive parameter space, but the high computational cost of conventional Technology Computer-Aided Design (TCAD) tools makes such wide-scale optimization impractical. To overcome these simulation barriers, we present a Physics-Informed Neural Operator (PINO)-based AI surrogate model designed for high-efficiency prediction of threshold voltage (Vth) shifts and retention behavior. By embedding fundamental physical principles into the learning architecture, our PINO framework achieves a speedup exceeding 10000x compared to TCAD while maintaining physical accuracy. The resulting surrogate provides a physics-consistent data engine for compact model parameter extraction and look-up-table (LUT) generation, directly supporting reliability-aware SPICE simulation of Fe-VNAND. This study demonstrates the model's effectiveness on a single FeFET configuration, serving as a pathway toward modeling the retention loss mechanisms.

cs.LG↗

arXiv2026

Shallow Trap States Control Electrical Performance of Amorphous Oxide Semiconductor Thin-Film Transistors

The performance of n-type amorphous oxide semiconductor thin-film transistors (TFTs) is largely controlled by the density of states (DoS) near the conduction band mobility edge. Here, the full subgap DoS of amorphous InGaZnO (a-IGZO) TFTs, used in display panels and dynamic random-access memory (DRAM) development, is measured by ultrabroadband photoconduction (UP-DoS) microscopy to within 0.1 eV of the mobility edge. The measured subgap DoS for 25 TFT processing conditions accurately predicts each transfer curve, showing how shallow defect states are electron traps that rigidly tune subthreshold swing, threshold voltage and drift mobility. For a set of TFTs, the subthreshold transfer characteristics can be independently simulated from the experimental shallow defect DoS, with no adjustable parameters. The full transfer curve is simulated by introducing a single parameter: the conduction band tail energy. Additionally, the simulation reveals that the shallow trap density controlling subthreshold behavior can be directly extracted from transfer curves. Finally, a systematic In-enrichment study, combined with DFT+U DoS simulations, enables identification of vacancy cation coordination environments for all experimentally observed subgap peaks. The dominant trap controlling conventional a-IGZO TFT performance is centered at ~0.32 eV below the conduction band mobility edge and is assigned to a Ga-Ga-In oxygen vacancy defect.

physics.app-ph↗

arXiv2025

Vertical NAND in a Ferroelectric-driven Paradigm Shift

Over the past decades, the relentless scaling and mass production of flash memory have underpinned the data-centric era. Yet charge-trap-based 3D NAND flash is now constrained by intrinsic physical and architectural limits, including reliability degradation at the device level, high operating power at the array level, and vertical scaling saturation at the system level. These bottlenecks hinder further advances in storage density and energy efficiency required by memory-centric computing. This Perspective outlines how coupling ferroelectric polarization with charge trapping can reconfigure the foundations of flash memory. In these hybrid architectures, polarization offers an energy-efficient pathway for charge modulation through enhanced Fowler-Nordheim tunneling, while trapped charges reinforce polarization-driven states to ensure stability. Such synergistic dynamics enable low-voltage operation and integration beyond one thousand layers without compromising process compatibility. We discuss the material, device, and architectural transitions required to realize this hybrid technology and chart future research directions to overcome the remaining scaling bottlenecks. Hybrid ferroelectric NAND extends conventional flash toward a scalable and energy-efficient platform, marking a paradigm shift for next-generation non-volatile memory.

physics.app-ph↗

arXiv2025

FeNOMS: Enhancing Open Modification Spectral Library Search with In-Storage Processing on Ferroelectric NAND (FeNAND) Flash

The rapid expansion of mass spectrometry (MS) data, now exceeding hundreds of terabytes, poses significant challenges for efficient, large-scale library search - a critical component for drug discovery. Traditional processors struggle to handle this data volume efficiently, making in-storage computing (ISP) a promising alternative. This work introduces an ISP architecture leveraging a 3D Ferroelectric NAND (FeNAND) structure, providing significantly higher density, faster speeds, and lower voltage requirements compared to traditional NAND flash. Despite its superior density, the NAND structure has not been widely utilized in ISP applications due to limited throughput associated with row-by-row reads from serially connected cells. To overcome these limitations, we integrate hyperdimensional computing (HDC), a brain-inspired paradigm that enables highly parallel processing with simple operations and strong error tolerance. By combining HDC with the proposed dual-bound approximate matching (D-BAM) distance metric, tailored to the FeNAND structure, we parallelize vector computations to enable efficient MS spectral library search, achieving 43x speedup and 21x higher energy efficiency over state-of-the-art 3D NAND methods, while maintaining comparable accuracy.

cs.AR↗

arXiv2025

An In-Situ Spatial-Temporal Sequence Detector for Neuromorphic Vision Sensor Empowered by High Density Vertical NAND Storage

Neuromorphic vision sensors require efficient real-time pattern recognition, yet conventional architectures struggle with energy and latency constraints. Here, we present a novel in-situ spatiotemporal sequence detector that leverages vertical NAND storage to achieve massively parallel pattern detection. By encoding each cell with two single-transistor-based multi-level cell (MLC) memory elements, such as ferroelectric field-effect transistors (FeFETs), and mapping a pixel's temporal sequence onto consecutive word lines (WLs), we enable direct temporal pattern detection within NAND strings. Each NAND string serves as a dedicated reference for a single pixel, while different blocks store patterns for distinct pixels, allowing large-scale spatial-temporal pattern recognition via simple direct bit-line (BL) sensing, a well-established operation in vertical NAND storage. We experimentally validate our approach at both the cell and array levels, demonstrating that vertical NAND-based detector achieves more than six orders of magnitude improvement in energy efficiency and more than three orders of magnitude reduction in latency compared to conventional CPU-based methods. These findings establish vertical NAND storage as a scalable and energy-efficient solution for next-generation neuromorphic vision processing.

cs.ET↗

arXiv2024

Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate

In this work, we propose a dual-port cell design to address the pass disturb in vertical NAND storage, which can pass signals through a dedicated and string-compatible pass gate. We demonstrate that: i) the pass disturb-free feature originates from weakening of the depolarization field by the pass bias at the high-${V}_{TH}$ (HVT) state and the screening of the applied field by channel at the low-${V}_{TH}$ (LVT) state; ii) combined simulations and experimental demonstrations of dual-port design verify the disturb-free operation in a NAND string, overcoming a key challenge in single-port designs; iii) the proposed design can be incorporated in a highly scaled vertical NAND FeFET string and the pass gate can be incorporated into the existing 3D NAND with the negligible overhead of the pass gate interconnection through a global bottom pass gate contact in the substrate.

cs.ET↗