arXiv subjects

David Jiménez

Publications and source records attributed to David Jiménez.

At least 37 records · Page 2Linked to original sources

arXiv2020

Experimental observation and modeling of the impact of traps on static and analog/HF performance of graphene transistors

The trap-induced hysteresis on the performance of a graphene field-effect transistor is experimentally diminished here by applying consecutive gate-to-source voltage pulses of opposing polarity. This measurement scheme is a practical and suitable approach to obtain reproducible device characteristics. Trap-affected and trap-free experimental data enable a discussion regarding the impact of traps on static and dynamic device performance. An analytical drain current model calibrated with the experimental data enables the study of the traps effects on the channel potential within the device. High-frequency figures of merit and the intrinsic gain of the device obtained from both experimental and synthetic data with and without hysteresis show the importance of considering the generally overlooked impact of traps for analog and high-frequency applications.

cond-mat.mes-hall↗

arXiv2020

Contact resistance assessment and high-frequency performance projection of black phosphorus field-effect transistor technologies

In this work, an evaluation of the contact quality of black phosphorus (BP) field-effect transistors (FETs) from different technologies previously reported is performed by means of an efficient and reliable contact resistance extraction methodology based on individual device practical characteristics. A good agreement is achieved between the extracted values with the Y-function method used here and reference values obtained with other methods considering internal values as well as with more expensive methods involving fabricated test structures. The method enables a direct evaluation of different steps in the same technology and it embraces the temperature dependence of the contact characteristics. Channel phenomena have no impact on the extracted contact resistance values. High-frequency performance projections are obtained for fabricated devices based on the extracted contact resistance.

cond-mat.mes-hall↗

arXiv2020

Small-signal parameters extraction and noise analysis of CNTFETs

The use of carbon nanotube (CNT) field-effect transistors (FETs) in microwave circuit design requires an appropriate, immediate and efficient description of their performance. This work describes a technique to extract the parameters of an electrical equivalent circuit for CNTFETs. The equivalent circuit is used to model the dynamic and noise performance at low- and high-frequency of different CNTFET technologies, considering extrinsic and intrinsic device parameters as well as the contact resistance. The estimation of the contact resistance at the metal/CNTs interfaces is obtained from a Y-function based extraction method. The noise model includes four noise sources: thermal noise, thermal channel noise, shot channel noise and flicker noise. The proposed model is compared with a compact model calibrated to hysteresis-free experimental data from a high-frequency multi-tube (MT)-CNTFET technology. Additionally, it has been applied to experimental data from another fabricated MT-CNTFET technology. The comparison in both cases shows a good agreement between reference data (simulation and experimental) and results from the proposed model. Low- and high-frequency noise projections of the fabricated reference device are further studied. Noise results from both studied technologies show that shot noise mainly contributes to the total noise due to the presence of Schottky barriers at contacts and along the channel.

physics.app-ph↗

arXiv2020

Accuracy of Y-function methods for parameters extraction of two-dimensional FETs across different technologies

The accuracy of contact resistance values of two-dimensional field-effect transistors extracted with the \textit{Y}-function considering the impact of the intrinsic mobility degradation is evaluated here. The difference between methodologies that take this factor into account and ignore it is pointed out by a detailed analysis of the approximations of the transport model used for each extraction. In contrast to the oftenly used approach where the intrinsic mobility degradation is neglected, a \textit{Y}-function-based method considering a more complete transport model yields contact resistance values similar to reference values obtained by other intricate approaches. The latter values are more suitable also to describe experimental data of two dimensional devices of different technologies. The intrinsic mobility degradation factor of two-dimensional transistors is experimentally characterized for the first time and its impact on the device performance is described and evaluated.

physics.app-ph↗

arXiv2020

Sensitivity Analysis of a Graphene Field-Effect Transistors by means of Design of Experiments

Graphene, due to its unique electronic structure favoring high carrier mobility, is considered a promising material for use in high-speed electronic devices in the post-silicon electronic era. For this reason, experimental research on graphene-based field-effect transistors (GFETs) has rapidly increased in the last years. However, despite the continuous progress in the optimization of such devices many critical issues remain to be solved such as their reproducibility and performance uniformity against possible variations originated by the manufacturing processes or the operating conditions. In the present work, changes of the ID-VDS characteristics of a Graphene Field-Effect Transistors, caused by a tolerance of 10% in the active channel (i.e. its length and width) and in the top oxide thickness are numerically investigated in order to assess the reliability of such devices. Design of Experiments (DoE) is adopted with the aim to identify the most influential factors on the electrical performance of the device, so that the fabrication process may be suitably optimized.

cond-mat.mes-hall↗

arXiv2020

The 2D pn Junction Driven Out-of-Equilibrium

The pn junction is a fundamental electrical component in modern electronics and optoelectronics. Currently, there is a great deal of interest in the two-dimensional (2D) pn junction. Although many experiments have demonstrated the working principle, there is a lack of fundamental understanding of its basic properties and expected performances, in particular when the device is driven out of equilibrium. To fill the current gap in understanding, we investigate the electrostatics and electronic transport of 2D lateral pn junctions. To do so we implement a physics-based simulator that selfconsistently solves the 2D Poisson's equation coupled to the drift-diffusion and continuity equations. Notably, the simulator takes into account the strong influence of the out of plane electric field through the surrounding dielectric, capturing the weak screening of charge carriers. Supported by simulations, we propose a Shockley-like equation for the ideal current voltage characteristics, in full analogy to the bulk junction after defining an effective depletion layer (EDL). We also discuss the impact of recombination generation processes inside the EDL, which actually produce a significant deviation with respect to the ideal behavior, consistently with experimental data. Moreover, we analyze the capacitances and conductance of the 2D lateral pn junction. Based on its equivalent circuit we investigate its cut-off frequency targeting RF applications. To gain deeper insight into the role played by material dimensionality, we benchmark the performances of single-layer MoS2 (2D) lateral pn junctions against those of the Si (3D) junction. Finally, a practical discussion on the short length 2D junction case together with the expected impact of interface states has been provided. Given the available list of 2D materials, this work opens the door to a wider exploration of material dependent performances.

physics.app-ph↗

arXiv2020

Contact resistance extraction of graphene FET technologies based on individual device characterization

Straightforward contact resistance extraction methods based on electrical device characteristics are described and applied here to graphene field-effect transistors from different technologies. The methods are an educated adaptation of extraction procedures originally developed for conventional transistors by exploiting the drift-diffusion-like transport in graphene devices under certain bias conditions. In contrast to other available approaches for contact resistance extraction of graphene transistors, the practical methods used here do not require either the fabrication of dedicated test structures or internal device phenomena characterization. The methodologies are evaluated with simulation-based data and applied to fabricated devices. The extracted values are close to the ones obtained with other more intricate methodologies. Bias-dependent contact and channel resistances studies, bias-dependent high-frequency performance studies and contact engineering studies are enhanced and evaluated by the extracted contact resistance values.

physics.app-ph↗

arXiv2020

Non-quasi-static effects in graphene field-effect transistors under high-frequency operation

We have investigated the non-quasi-static (NQS) effects in graphene field-effect transistors (GFETs), which are relevant for GFET operation at high frequencies as a result of significant carrier inertia. A small-signal NQS model is derived from the analytical solution of drift-diffusion equation coupled with the continuity equation, which can be expressed in terms of modified Bessel functions of the first kind. The NQS model can be conveniently simplified to provide an equivalent circuit of lumped elements ready to be used in standard circuit simulators. Taking into account only first-order NQS effects, accurate GFET based circuit simulations up to several times the cut-off frequency (fT) can be performed. Notably, it reduces to the quasi-static (QS) approach when the operation frequency is below ~fT/4. To validate the NQS model, we have compared its outcome against simulations based on a multisegment approach consisting of breaking down the channel length in N equal segments described by the QS model each one.

physics.app-ph↗

arXiv2020

Large-signal model of 2DFETs: compact modeling of terminal charges and intrinsic capacitances

We present a physics-based circuit-compatible model for double-gated two-dimensional semiconductor based field effect transistors, which provides explicit expressions for the drain current, terminal charges and intrinsic capacitances. The drain current model is based on the drift-diffusion mechanism for the carrier transport and considers Fermi-Dirac statistics coupled with an appropriate field-effect approach. The terminal charge and intrinsic capacitance models are calculated adopting a Ward-Dutton linear charge partition scheme that guarantees charge-conservation. It has been implemented in Verilog-A to make it compatible with standard circuit simulators. In order to benchmark the proposed modeling framework we also present experimental DC and high-frequency measurements of a purposely fabricated monolayer MoS2 FET showing excellent agreement between the model and the experiment and thus demonstrating the capabilities of the combined approach to predict the performance of 2DFETs.

cond-mat.mes-hall↗

arXiv2019

Does carrier velocity saturation help to enhance fmax in graphene field-effect transistors?

It has been argued that current saturation in graphene field-effect transistors (GFETs) is needed to get the highest possible maximum oscillation frequency (fmax). This paper numerically investigates whether velocity saturation can help to get better current saturation and if that correlates with enhanced fmax. For such a purpose, we used a drift-diffusion simulator that includes several factors that influence output conductance, especially at short channel lengths and-or large drain bias: short-channel electrostatics, saturation velocity, graphene-dielectric interface traps, and self-heating effects. As a testbed for our investigation, we analyzed fabricated GFETs with high extrinsin cutoff frequency fT,x (34 GHz) and fmax (37 GHz). Our simulations allow for a microscopic (local) analysis of the channel parameteres such as carrier concentration, drift and saturation velocities. For biases far away from the Dirac voltage, where the channel behaves as unipolar, we confirmed that the higher is the drift velocity, as close as possible to the saturation velocity, the greater fmax is. However, the largest fmax is recorded at biases near the crossover between unipolar and bipolar behavior, where it does not hold that the highest drift velocity maximizes fmax. In fact, the position and magnitude of the largest fmax depend on the complex interplay between the carrier concentration and total velocity which, in turn, are impacted by the self-heating. Importantly, this effect was found to severely limit radio-frequency performance, reducing the maximum fmax from around 60 to 40 GHz.

physics.app-ph↗

arXiv2019

Velocity Saturation effect on Low Frequency Noise in short channel Single Layer Graphene FETs

Graphene devices for analog and RF applications are prone to Low Frequency Noise (LFN) due to its upconversion to undesired phase noise at higher frequencies. Such applications demand the use of short channel graphene transistors that operate at high electric fields in order to ensure a high speed. Electric field is inversely proportional to device length and proportional to channel potential so it gets maximized as the drain voltage increases and the transistor length shrinks. Under these conditions though, short channel effects like Velocity Saturation (VS) should be taken into account. Carrier number and mobility fluctuations have been proved to be the main sources that generate LFN in graphene devices. While their contribution to the bias dependence of LFN in long channels has been thoroughly investigated, the way in which VS phenomenon affects LFN in short channel devices under high drain voltage conditions has not been well understood. At low electric field operation, VS effect is negligible since carriers velocity is far away from being saturated. Under these conditions, LFN can be precicely predicted by a recently established physics-based analytical model. The present paper goes a step furher and proposes a new model which deals with the contribution of VS effect on LFN under high electric field conditions. The implemented model is validated with novel experimental data, published for the first time, from CVD grown back-gated single layer graphene transistors operating at gigahertz frequencies. The model accurately captures the reduction of LFN especially near charge neutrality point because of the effect of VS mechanism. Moreover, an analytical expression for the effect of contact resistance on LFN is derived. This contact resistance contribution is experimentally shown to be dominant at higher gate voltages and is accurately described by the proposed model.

cond-mat.mes-hall↗

arXiv2019

Large-signal model of the Metal-Insulator-Graphene diode targeting RF applications

We present a circuit-design compatible large-signal compact model of metal-insulator-graphene (MIG) diodes for describing its dynamic response for the first time. The model essentially consists of a voltage-dependent diode intrinsic capacitance coupled with a static voltage-dependent current source, the latter accounts for the vertical electron transport from/towards graphene, which has been modeled by means of the Dirac-thermionic electron transport theory through the insulator barrier. Importantly, the image force effect has been found to play a key role in determining the barrier height, so it has been incorporated into the model accordingly. The resulting model has been implemented in Verilog A to be used in existing circuit simulators and benchmarked against an experimental 6-nm TiO2 barrier MIG diode working as a power detector.

physics.app-ph↗

arXiv2019

Electrostatics of Two-Dimensional Lateral Junctions

The increasing technological control of two-dimensional materials has allowed the demonstration of 2D lateral junctions, which display unique properties that might serve as the basis for a new generation of 2D electronic and optoelectronic devices. Notably, the chemically doped MoS$_2$ homojunction, the WSe$_2$-MoS$_2$ monolayer and MoS$_2$ monolayer/multilayer heterojunctions, have been demonstrated. Here we report the investigation of 2D lateral junction electrostatics, which differs from the bulk case because of the weaker screening, producing a much longer transition region between the space charge region and the quasi-neutral region, making inappropriate the use of the complete-depletion approximation. For such a purpose we have developed a method based on the conformal mapping technique to solve the 2D electrostatics, which is widely applicable to every kind of junctions, giving accurate results for even large asymmetric charge distribution scenarios.

cond-mat.mes-hall↗

arXiv2019

Radio frequency performance projection and stability trade-off of h-BN encapsulated graphene field-effect transistors

Hexagonal boron nitride (h-BN) encapsulation significantly improves carrier transport in graphene. This work investigates the benefit of implementing the encapsulation technique in graphene field-effect transistors (GFET) in terms of their radio frequency (RF) performance. For such a purpose, a drift-diffusion self-consistent simulator is prepared to get the GFET electrical characteristics. Both the mobility and saturation velocity information are obtained by means of an ensemble Monte Carlo simulator upon considering the relevant scattering mechanisms that affect carrier transport. RF figures of merit are simulated using an accurate small-signal model that includes non-reciprocal capacitances. Results reveal that the cutoff frequency could scale up to the physical limit given by the inverse of the transit time. Projected maximum oscillation frequencies, in the order of few THz, are expected to exceed the values demonstrated by InP and Si based RF transistors. The existing trade-off between power gain and stability and the role played by the gate resistance are also studied. High power gain and stability are feasible even if the device is operated far away from current saturation. Finally, the benefits of device unilateralization and the exploitation of the negative differential resistance region to get negative-resistance gain are discussed.

cond-mat.mes-hall↗

arXiv2018

Understanding the Bias Dependence of Low Frequency Noise in Sin-gle Layer Graphene FETs

This letter investigates the bias-dependent low frequency noise of single layer graphene field-effect transistors. Noise measurements have been conducted with electrolyte-gated graphene transistors covering a wide range of gate and drain bias conditions for different channel lengths. A new analytical model that accounts for the propagation of the local noise sources in the channel to the terminal currents and voltages is proposed in this paper to investigate the noise bias dependence. Carrier number and mobility fluctuations are considered as the main causes of low frequency noise and the way these mechanisms contribute to the bias dependence of the noise is analyzed in this work. Typically, normalized low frequency noise in graphene devices has been usually shown to follow an M-shape dependence versus gate voltage with the minimum near the charge neutrality point (CNP). Our work reveals for the first time the strong correlation between this gate dependence and the residual charge which is relevant in the vicinity of this specific bias point. We discuss how charge inhomogeneity in the graphene channel at higher drain voltages can contribute to low frequency noise; thus, channel regions nearby the source and drain terminals are found to dominate the total noise for gate biases close to the CNP. The excellent agreement between the experimental data and the predictions of the analytical model at all bias conditions confirms that the two fundamental 1/f noise mechanisms, carrier number and mobility fluctuations, must be considered simultaneously to properly understand the low frequency noise in graphene FETs. The proposed analytical compact model can be easily implemented and integrated in circuit simulators, which can be of high importance for graphene based circuits design.

cond-mat.mes-hall↗

arXiv2017

Scaling of graphene field-effect transistors supported on hexagonal boron nitride: radio-frequency stability as a limiting factor

The quality of graphene in nanodevices has increased hugely thanks to the use of hexagonal boron nitride as a supporting layer. This paper studies to which extent hBN together with channel length scaling can be exploited in graphene field effect transistors (GFETs) to get a competitive radio frequency (RF) performance. Carrier mobility and saturation velocity were obtained from an ensemble Monte Carlo simulator that accounted for the relevant scattering mechanisms (intrinsic phonons, scattering with impurities and defects, etc.). This information is fed into a self consistent simulator, which solves the drift diffusion equation coupled with the two dimensional Poisson's equation to take full account of short channel effects. Simulated GFET characteristics were benchmarked against experimental data from our fabricated devices. Our simulations show that scalability is supposed to bring to RF performance an improvement that is, however, highly limited by instability. Despite the possibility of a lower performance, a careful choice of the bias point can avoid instability. Nevertheless, maximum oscillation frequencies are still achievable in the THz region for channel lengths of a few hundreds of nanometers.

physics.app-ph↗

arXiv2017

Small-signal model for 2D-material based field-effect transistors targeting radio-frequency applications: the importance of considering non-reciprocal capacitances

A small-signal equivalent circuit of 2D-material based field-effect transistors is presented. Charge conservation and non-reciprocal capacitances have been assumed so the model can be used to make reliable predictions at both device and circuit levels. In this context, explicit and exact analytical expressions of the main radio-frequency figures of merit of these devices are given. Moreover, a direct parameter extraction methodology is provided based on S-parameter measurements. In addition to the intrinsic capacitances, transconductance and output conductance, our approach allows extracting the series combination of drain/source metal contact and access resistances. Accounting for these extrinsic resistances is of upmost importance when dealing with low dimensional field-effect transistors.

cond-mat.mes-hall↗

arXiv2016

The role of the Fermi level pinning in gate tunable graphene-semiconductor junctions

Graphene based transistors relying on a conventional structure cannot switch properly because of the absence of an energy gap in graphene. To overcome this limitation, a barristor device was proposed, whose operation is based on the modulation of the graphene-semiconductor (GS) Schottky barrier by means of a top gate, and demonstrating an ON-OFF current ratio up to $10^5$. Such a large number is likely due to the realization of an ultra clean interface with virtually no interface trapped charge. However, it is indeed technologically relevant to know the impact that the interface trapped charges might have on the barristor's electrical properties. We have developed a physics based model of the gate tunable GS heterostructure where non-idealities such as Fermi Level Pinning (FLP) and a "bias dependent barrier lowering effect" has been considered. Using the model we have made a comprehensive study of the barristor's expected digital performance.

cond-mat.mes-hall↗