arXiv subjects
Publications and source records attributed to J. Ye.
In this write-up we focus on fast data links that read out particle detectors. This includes developments of ASICs, optical modules, identifying passive components such as fiber and connector, and a link system design. A review of the current status is provided. The goal of R\&D is to double (near term) and quadruple (longer term) the present data transmission rate for particle detectors, enabling a wide range of physics exploration and measurements.
We present the design and the test results of a quad-channel optical transceiver module (QTRx) possibly for future particle physics experiments. The transmitters of QTRx, each at 10 Gbps, are based on a Quad-channel VCSEL Diode array Driver (QLDD) and 1 x 4 VCSEL array. The receivers of QTRx, with data rates of 2.56 Gbps or 10 Gbps per channel, are based on a Quad-channel Trans-Impedance and limiting Amplifier (QTIA) and 1 x 4 photodiode array of GaAs or InGaAs. QTRx is 20 mm x 10 mm x 5 mm and couples to an MT fiber connector. Test results indicate that QTRx achieves the design goals with a power consumption of 124 mW per transmitter channel at 10 Gbps and 120 mW at 2.56 Gbps for the receiver channel with an on-chip charge pump. The sensitivities of QTIA are -17 dBm at 2.56 Gbps and -8 dBm at 10 Gbps, respectively. Further improvements with a gold-finger interface and a more compact optical lens are being designed.
A prototype optical-link board has been developed for the ATLAS Liquid Argon Calorimeter Phase-2 upgrade. The board consists of 24 lpGBT chips and 8 VTRx+ modules and demonstrates the full optical link design of the future front-end board. The board has 22 simplex optical links to transmit detector data, which are emulated in FPGAs and injected through 6 FMC connectors, to the off-detector electronics. The board implements 2 duplex optical links for clocks, control, and monitoring with redundant design to improve the system reliability. Data transmission and all redundant designs have been verified. A fiber routing scheme, in which 2 or 3 VTRx+ modules are re-connected to the front panel with an MPO connector, has been prototyped.
We proposed a novel method for exploring the intrinsic energy resolution of a liquid scintillator (LAB + 2.5 g/L PPO + 3 mg/L bis-MSB) for approximately 1 MeV electrons. With the help of coincidence detection technology, single-energy electrons of Bi 207 were effectively selected. With careful measurement and analysis of the energy resolution of a small liquid scintillator detector, the intrinsic energy resolution to 976 keV electrons was extracted to be 1.83%. We used the wide-angle Compton coincidence (WACC) method to measure the luminescent nonlinearity of the liquid scintillator and found that it contributes only weakly to the intrinsic energy resolution of electrons. Such an unexpected large intrinsic energy resolution may come from fluctuations in energy transfer processes.
We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear energy transfer (LET) from 1.3 to 62.5 MeV*cm^2/mg.
The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed the lab tests with GaAs photodiodes.
We present the design and test results of a novel data transmitter ASIC operating up to 20.48 Gbps with 4-level Pulse-Amplitude-Modulation (PAM4) for particle physics experiments. This ASIC, named GBS20, is fabricated in a 65 nm CMOS technology. Two serializers share a 5.12 GHz Phase Locked Loop (PLL) clock. The outputs from the serializers are combined into a PAM4 signal that directly drives a Vertical-Cavity-Surface-Emitting-Laser (VCSEL). The input data channels, each at 1.28 Gbps, are scrambled with an internal 27-1 Pseudo-Random Binary Sequence (PRBS), which also serves as a frame aligner. GBS20 is tested to work at 10.24 and 20.48 Gbps with a VCSEL-based Transmitter-Optical-Subassembly (TOSA). The power consumption of GBS20 is below 238 mW and reduced to 164 mW in the low-power mode.
We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 uW and 10.4 uW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16x16 pixel matrix.
We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16x16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the preamplifier and the discriminator. The preamplifier handles the LGAD charge signal with the most probable value of around 15 fC. The discriminator generates the digital pulse, which provides the Time-Of-Arrival (TOA, leading edge) and Time-Over-Threshold (TOT, pulse width) information. The prototype of ETROC (ETROC0) that implements a single channel of analog readout circuits has been evaluated with charge injection. The jitter of the analog readout circuits, measured from the discriminator's leading edge, is better than 16 ps for a charge larger than 15 fC with the sensor capacitance. The time walk resulting from different pulse heights can be corrected using the TOT measurement. The time resolution distribution has a standard deviation of 29 ps after the time-walk correction from the charge injection. At room temperature, the preamplifier's power consumption is measured to be 0.74 mW and 1.53 mW per pixel in the low- and high-power mode, respectively. The measured power consumption of the discriminator is 0.84 mW per pixel. With the ASIC alone or the LGAD sensor, The characterization performances fulfill the ETL's challenging requirements.
We present the procedures and results of the quality control tests for the front-end optical link components in the ATLAS Liquid Argon Calorimeter Phase-1 upgrade. The components include a Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC LOCld, custom optical transmitter/transceiver modules MTx/MTRx, and a transmitter ASIC LOCx2. LOCld, MTx, and LOCx2 each contain two channels with the same structure, while MTRx has a transmitter channel and a receiver channel. Each channel is tested at 5.12 Gbps. A total of 5341 LOCld chips, 3275 MTx modules, 797 MTRx modules, and 3198 LOCx2 chips are qualified. The yields are 73.9%, 98.0%, 98.4%, and 61.9% for LOCld, LOCx2, MTx, and MTRx, respectively.
We present the characterization and quality control test of a gigabit cable receiver ASIC prototype, GBCR2, for the ATLAS Inner Tracker pixel detector upgrade. GBCR2 equalizes and retimes the uplink electrical signals from RD53B through a 6 m Twinax AWG34 cable to lpGBT. GBCR2 also pre-emphasizes downlink command signals through the same electrical connection from lpGBT to RD53B. GBCR2 has seven uplink channels each at 1.28 Gbps and two downlink channels each at 160 Mbps. The prototype is fabricated in a 65 nm CMOS process. The characterization of GBCR2 has been demonstrated that the total jitter of the output signal is 129.1 ps (peak-peak) in the non-retiming mode or 79.3 ps (peak-peak) in the retiming mode for the uplink channel and meets the requirements of lpGBT. The total power consumption of all uplink channels is 87.0 mW in the non-retiming mode and 101.4 mW in the retiming mode, below the specification of 174 mW. The two downlink channels consume less than 53 mW. A quality control test procedure is proposed and 169 prototype chips are tested. The yield is about 97.0%.
Hyperbolic geometry has been successfully applied in modeling brain cortical and subcortical surfaces with general topological structures. However such approaches, similar to other surface based brain morphology analysis methods, usually generate high dimensional features. It limits their statistical power in cognitive decline prediction research, especially in datasets with limited subject numbers. To address the above limitation, we propose a novel framework termed as hyperbolic stochastic coding (HSC). Our preliminary experimental results show that our algorithm achieves superior results on various classification tasks. Our work may enrich surface based brain imaging research tools and potentially result in a diagnostic and prognostic indicator to be useful in individualized treatment strategies.
Dipole-dipole interactions lead to frequency shifts that are expected to limit the performance of next-generation atomic clocks. In this work, we compute dipolar frequency shifts accounting for the intrinsic atomic multilevel structure in standard Ramsey spectroscopy. When interrogating the transitions featuring the smallest Clebsch-Gordan coefficients, we find that a simplified two-level treatment becomes inappropriate, even in the presence of large Zeeman shifts. For these cases, we show a net suppression of dipolar frequency shifts and the emergence of dominant non-classical effects for experimentally relevant parameters. Our findings are pertinent to current generations of optical lattice and optical tweezer clocks, opening a way to further increase their current accuracy, and thus their potential to probe fundamental and many-body physics.
We present a novel design and the test results of a 4-channel driver for an array of Vertical-Cavity Surface-Emitting Lasers (VCSELs). This ASIC, named cpVLAD and fabricated in a 65 nm CMOS technology, has on-chip charge pumps and is for data rates up to 10 Gbps per channel. The charge pumps are implemented to address the issue of voltage margin of the VCSEL driving stage in the applications under low temperature and harsh radiation environment. Test results indicate that cpVLAD is capable of driving VCSELs with forward voltages of up to 2.8 V using 1.2 V and 2.5 V power supplies with a power consumption of 94 mW/channel.
The ATLAS phase-I upgrade aims to enhance event trigger performance in the Liquid Argon (LAr) calorimeter and the forward muon spectrometer. The trigger signals are transmitted by optical transceivers at 5.12 Gbps per channel in a radiation field. We report the design, quality control in production and ageing test of the transceivers fabricated with the LOCld laser driver and multi-mode 850 nm vertical-cavity surface-emitting laser (VCSEL). The modules are packaged in miniature formats of dual-channel transmitter (MTx) and transceiver (MTRx) for the LAr. The transmitters are also packaged in small form-factor pluggable (SFP) for the muon spectrometer. In production, the LOCld chips and VCSELs in TOSA package were examined before assembly. All of the modules were tested and selected during production for quality control based on the eye-diagram parameters measured at 5.12 Gbps. The yield is 98 % for both the MTx and MTRx on a total 4.7k modules. The uniformity of transmitter channels of a MTx was assured by choosing the TOSA components with approximately equal light powers. The ageing effect is monitored in burn-in of a small batch of transmitter modules with bit-error test and eye-diagrams measured periodically. The observables are stable with the light power degradation within 5 % over a period of more than 6k hours.
This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver channels and a downstream transmitter channel. Each upstream channel operates at 5.12 Gbps, while the downstream channel operates at 2.56 Gbps. In each upstream channel, GBCR equalizes a signal received through a 5-meter 34-American Wire Gauge (AWG) twin-axial cable, retimes the data with a recovered clock, and drives an optical transmitter. In the downstream channel, GBCR receives the data from an optical receiver and drives the same type of cable as the upstream channels. The output jitter of an upstream channel is 26.5 ps and the jitter of the downstream channel after the cable is 33.5 ps. Each upstream channel consumes 78 mW and each downstream channel consumes 27 mW. Simulation results of the upstream test channel suggest that a significant jitter reduction could be achieved with minimally increased power consumption by using a Feed Forward Equalizer (FFE) + Decision Feedback Equalization (DFE) in addition to the linear equalization of the baseline channel. GBCR is designed in a 65-nm CMOS technology.
We present the design and test results of a 4-channel 10-Gbps/ch Vertical-Cavity Surface-Emitting Laser array driver, the cpVLAD. With on-chip charge-pumps to extend the biasing headroom for the VCSELs needed for low temperature operation and mitigation of the radiation effects. The cpVLAD was fabricated in a 65-nm CMOS technology. The test results show that the cpVLAD is capable of driving VCSELs with forward bias voltages as high as 2.8 V from a 2.5 V power supply. The power consumption of the cpVLAD is 94 mW/ch.
We present a dual-channel optical transmitter (MTx+)/transceiver (MTRx+) for the front-end readout electronics of high-energy physics experiments. MTx+ utilizes two Transmitter Optical Sub-Assemblies (TOSAs) and MTRx+ utilizes a TOSA and a Receiver Optical Sub-Assemblies (ROSA). Both MTx+ and MTRx+ receive multimode fibers with standard Lucent Connectors (LCs) as the optical interface and can be panel or board mounted to a motherboard with a standard Enhanced Small Form-factor Pluggable (SFP+) connector as the electrical interface. MTx+ and MTRx+ employ a dual-channel Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC called LOCld65, which brings the transmitting data rate up to 14 Gbps per channel. MTx+ and MTRx+ have been tested to survive 4.9 kGy(SiO2).