arXiv subjects

Joerg Appenzeller

Publications and source records attributed to Joerg Appenzeller.

At least 19 recordsLinked to original sources

arXiv2026

Process-Technology Co-optimization for 2D-FETs

We present the first experimental machine learning (ML)-enabled Process-Technology Co-Optimization (PTCO) framework for optimizing 2D transition metal dichalcogenide (TMD) FET fabrication directly from statistically meaningful experimental data rather than pure simulation data. We first introduce a transition voltage metric, VTrans, to quantify the gate voltage required for off-to-on switching and reveal its direct correlation with subthreshold swing (SS), highlighting an overlooked switching characteristic that governs both off-state and on-state performance. By integrating automated metric extraction, multi-objective recipe ranking, and predictive modeling, our framework uncovers hidden process-performance correlations and predicts the performance of unexplored fabrication recipes from limited experimental data. Experimental validation shows close agreement with ML predictions, thus demonstrating the framework's ability to efficiently guide gate stack optimization through iterative experimental feedback.

cond-mat.mes-hall↗

arXiv2026

Spin Vector Control for Heisenberg-Inspired Probabilistic Computing

Probabilistic bits (p-bits) have emerged as a cornerstone of probabilistic computing, enabling energy-efficient hardware implementation for probabilistic inference and combinatorial optimization. A critical challenge in advancing this field beyond binary p-bits lies in realizing and manipulating vector spin information, essential for mapping complex energy-based models such as the Heisenberg Hamiltonian.Here, we demonstrate a spintronic platform capable of real-space vector summation by using dual ferromagnetic spin injections into a monolayer graphene channel. By electrically tuning the spin polarization through independently controlled injection currents, we achieve continuous control over the magnitude and direction of the resulting spin accumulation vector. Experimental observations, supported by theoretical vector summation models and spin-circuit simulations, reveal coherent vector interactions and angular tunability of the spin state. This approach enables direct implementation of vector-based spin logic and lays the groundwork for mapping classical Heisenberg models using stochastic low-barrier magnets. Our results establish a scalable pathway for realizing probabilistic spin circuits based on two-dimensional materials, offering new opportunities for low-power, non-Boolean computing architectures.

cond-mat.mes-hall↗

arXiv2026

Seed Layer Engineering for Effective Charge Transfer Doping of MoS$_2$ Transistors

Integrating two-dimensional semiconductors such as MoS$_2$ with dielectric materials remains a central challenge for their use in future logic technologies. While seed layers are typically introduced to promote dielectric nucleation and adhesion, we show that they also critically govern charge-transfer doping and, in turn, transistor performance. Back-gated monolayer MoS$_2$ transistors passivated on their top-surface with a Ta-seed/HfO$_x$ dielectric stack were fabricated and characterized electrically and physically using Raman, photoluminescence, and X-ray photoelectron spectroscopies. Threshold voltage and on-current varied strongly with Ta-seed thickness and deposition conditions, and these changes correlated with signatures observed across all spectroscopic probes. The results reveal that the seed layer both introduces disorder into the MoS$_2$ channel and modifies the interfacial charge environment controlling charge transfer between HfO$_x$ and MoS$_2$. Optical spectroscopy shows that on-current tracks seed-induced disorder, whereas X-ray photoelectron spectroscopy indicates that threshold voltage correlates with shifts in the local electrostatic environment associated with interfacial charge transfer. Better performance was obtained with ultrathin 0.2 nm Ta seed layers deposited under oxygen-poor conditions, which limit deposition-induced damage while facilitating charge transfer. These findings identify seed-layer engineering as a key strategy for controlling disorder and interfacial doping in MoS$_2$ devices and establish multimodal spectroscopy as a practical during-fabrication approach for process development and monitoring.

cond-mat.mtrl-sci↗

arXiv2026

Scaling Two-Dimensional Semiconductor Nanoribbons for High-Performance Electronics

As silicon transistors scale toward future technology nodes, three-dimensional architectures -- including gate-all-around (GAA) nanoribbon and complementary field-effect transistors (CFETs) -- require channel widths in the tens of nanometers to meet density targets. Monolayer transition metal dichalcogenides (TMDs), with their atomically thin bodies, are promising channel materials for these architectures, yet most TMD-based FETs remain limited to micrometer-scale widths. Here, we show that channel width scaling of monolayer MoS2 nanoribbon transistors not only preserves but also enhances device performance. Reducing the channel width from hundreds of nanometers to $\sim$30--40 nm increases the median on-current density by $\sim$42% and reduces the median subthreshold swing by $\sim$16%, with a champion device reaching 995 $μ$A $μ$m$^{-1}$ at a drain-to-source voltage of 1 V and an overdrive voltage of 2.5 V. We attribute these improvements to three mechanisms: minimal edge-induced disorder, enhanced gate electrostatics at ribbon edges, and more efficient side-contact injection, together reducing contact resistance from $\sim$860 $Ω$ $μ$m to $\sim$270 $Ω$ $μ$m. Extending the platform to n-type WS2 and p-type WSe2 FETs, we achieve WSe2 p-FET on-currents of 357 $μ$A $μ$m$^{-1}$. These findings suggest that monolayer TMD nanoribbon FETs are promising candidates for future ultra-scaled electronics.

cond-mat.mtrl-sci↗

arXiv2026

Experimental Demonstration of an On-Chip CMOS-Integrated 3T-1MTJ Probabilistic Bit -- A P-Bit

Ongoing semiconductor scaling challenges and the rise of neuromorphic computing have sparked interest in exploring novel computing schemes to achieve higher power efficiency and computational capabilities. Probabilistic computing is one candidate that endows low power consumption, capability of solving probability-encoded computational problems, and the ease of integration with existing CMOS technology. A basic building block of this scheme is the probabilistic bit (P-Bit), which utilizes a novel device such as a stochastic magnetic tunnel junction (sMTJ) to generate tunable randomness by nature. This work presents the first experimental demonstration of a fully CMOS-integrated sMTJ-based P-Bit, capable of generating rail-to-rail stochastic output with a mere collection of 3 transistors + 1 sMTJ. Furthermore, simulations also confirm this P-Bit's functionality in probabilistic logic circuits. The demonstration of such P-Bit paves the way towards realizing monolithic large-scale probabilistic computing architecture on CMOS chips.

cs.ET↗

arXiv2023

Tailoring Amorphous Boron Nitride for High-Performance 2D Electronics

Two-dimensional (2D) materials have garnered significant attention in recent years due to their atomically thin structure and unique electronic and optoelectronic properties. To harness their full potential for applications in next-generation electronics and photonics, precise control over the dielectric environment surrounding the 2D material is critical. The lack of nucleation sites on 2D surfaces to form thin, uniform dielectric layers often leads to interfacial defects that degrade the device performance, posing a major roadblock in the realization of 2D-based devices. Here, we demonstrate a wafer-scale, low-temperature process (< 250 °C) using atomic layer deposition (ALD) for the synthesis of uniform, conformal amorphous boron nitride (aBN) thin films. ALD deposition temperatures between 125 and 250 °C result in stoichiometric films with high oxidative stability, yielding a dielectric strength of 8.2 MV/cm. Utilizing a seed-free ALD approach, we form uniform aBN dielectric layers on 2D surfaces and fabricate multiple quantum well structures of aBN/MoS2 and aBN-encapsulated double-gated monolayer (ML) MoS2 field-effect transistors to evaluate the impact of aBN dielectric environment on MoS2 optoelectronic and electronic properties. Our work in scalable aBN dielectric integration paves a way towards realizing the theoretical performance of 2D materials for next-generation electronics.

cond-mat.mtrl-sci↗

arXiv2023

Experimental demonstration of an integrated on-chip p-bit core utilizing stochastic Magnetic Tunnel Junctions and 2D-MoS2 FETs

Probabilistic computing is a novel computing scheme that offers a more efficient approach than conventional CMOS-based logic in a variety of applications ranging from optimization to Bayesian inference, and invertible Boolean logic. The probabilistic-bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires tunable stochasticity; by coupling low-barrier stochastic Magnetic Tunnel Junctions (MTJs) with a transistor circuit, a compact implementation is achieved. In this work, through integrating stochastic MTJs with 2D-MoS$_{2}$ FETs, the first on-chip realization of a key p-bit building block displaying voltage-controllable stochasticity is demonstrated. In addition, supported by circuit simulations, this work provides a careful analysis of the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component influence the overall p-bit output. This understanding of the interplay between the characteristics of the transistors and the MTJ is vital for the construction of a fully functioning p-bit, making the design rules presented in this article key for future experimental implementations of scaled on-chip p-bit networks.

cond-mat.mes-hall↗

arXiv2023

A Magnetoelectric Memory Device Based on Pseudo-Magnetization

We propose a new type of magnetoelectric memory device that stores magnetic easy-axis information or pseudo-magnetization, rather than a definite magnetization direction, in piezoelectric/ferromagnetic (PE/FM) heterostructures. Theoretically, we show how a PE/FM combination can lead to non-volatility in pseudo-magnetization exhibiting ferroelectric-like behavior. The pseudo-magnetization can be manipulated by extremely low voltages especially when the FM is a low-barrier nanomagnet. Using a circuit model benchmarked against experiments, we determine the switching energy, delay, switching probability and retention time of the envisioned 1T/1C memory device in terms of magnetic and circuit parameters and discuss its thermal stability in terms of a key parameter called back-voltage vm which is an electrical measure of the strain-induced magnetic field. Taking advantage of ferromagnetic resonance (FMR) measurements, we experimentally extract values for vm in CoFeB films and circular nano-magnets deposited on Pb(Mg1/3Nb2/3)0.7Ti0.3O3 (PMN-PT) which agree well with the theoretical values. Our experimental findings indeed indicate the feasibility of the proposed novel device and confirm the assumed parameters in our modeling effort.

physics.app-ph↗

arXiv2022

How to Report and Benchmark Emerging Field-Effect Transistors

Emerging low-dimensional nanomaterials have been studied for decades in device applications as field-effect transistors (FETs). However, properly reporting and comparing device performance has been challenging due to the involvement and interlinking of multiple device parameters. More importantly, the interdisciplinarity of this research community results in a lack of consistent reporting and benchmarking guidelines. Here we report a consensus among the authors regarding guidelines for reporting and benchmarking important FET parameters and performance metrics. We provide an example of this reporting and benchmarking process for a two-dimensional (2D) semiconductor FET. Our consensus will help promote an improved approach for assessing device performance in emerging FETs, thus aiding the field to progress more consistently and meaningfully.

cond-mat.mtrl-sci↗

arXiv2022

Design Considerations for 2D Dirac-Source FETs: Device Parameters, Non-Idealities and Benchmarking

Dirac-source field-effect transistors (DS-FETs) have been proposed as promising candidates for low-power switching devices by leveraging the Dirac cone of graphene as a low-pass energy filter. In particular, using two-dimensional (2D) materials as the channel in a DS-FET is of interest for ultimate scaling purposes. In this paper, we investigate the design considerations for 2D DS-FETs using ballistic simulations based on Landauer formalism. We study the impact of several key device parameters on the device performance, such as graphene doping, Schottky barrier heights, and effective mass of the 2D channel. In addition, we study the impact of non-idealities on the performance of DS-FETs, such as graphene disorder and rethermalization, as well as ways to mitigate them. Finally, we benchmark the performance of DS-FETs for different channel materials, providing a guide for the proper choice of material for 2D DS-FETs.

cond-mat.mes-hall↗

arXiv2021

Electric field control of interaction between magnons and quantum spin defects

Hybrid systems coupling quantum spin defects (QSD) and magnons can enable unique spintronic device functionalities and probes for magnetism. Here, we add electric field control of magnon-QSD coupling to such systems by integrating ferromagnet-ferroelectric multiferroic with nitrogen-vacancy (NV) center spins. Combining quantum relaxometry with ferromagnetic resonance measurements and analytical modeling, we reveal that the observed electric-field tuning results from ferroelectric polarization control of the magnon-generated fields at the NV. Exploiting the demonstrated control, we also propose magnon-enhanced hybrid electric field sensors with improved sensitivity.

cond-mat.mes-hall↗

arXiv2020

Sub-60 mV/decade switching in a metal-insulator-metal-insulator-semiconductor transistor without ferroelectric component

Negative capacitance field-effect transistors (NC-FETs) have attracted wide interest as promising candidates for steep-slope devices, and sub-60 mV/decade switching has been demonstrated in NC-FETs with various device structures and material systems. However, the detailed mechanisms of the observed steep-slope switching in some of these experiments are under intense debate. Here we show that sub-60 mV/decade switching can be observed in a WS2 transistor with a metal-insulator-metal-insulator-semiconductor (MIMIS) structure - without any ferroelectric component. This structure resembles an NC-FET with internal gate, except that the ferroelectric layer is replaced by a leaky dielectric layer. Through simulations of the charging dynamics during the device characterization using an RC network model, we show that the observed steep-slope switching in our "ferroelectric-free" transistors can be attributed to the internal gate voltage response to the chosen varying gate voltage scan rates. We further show that a constant gate voltage scan rate can also lead to transient sub-60 mV/decade switching in an MIMIS structure with voltage dependent internal gate capacitance. Our results indicate that the observation of sub-60 mV/decade switching alone is not sufficient evidence for the successful demonstration of a true steep-slope switching device and that experimentalists need to critically assess their measurement setups to avoid measurement-related artefacts.

cond-mat.mes-hall↗

arXiv2020

Hardware implementation of Bayesian network building blocks with stochastic spintronic devices

Bayesian networks are powerful statistical models to understand causal relationships in real-world probabilistic problems such as diagnosis, forecasting, computer vision, etc. For systems that involve complex causal dependencies among many variables, the complexity of the associated Bayesian networks become computationally intractable. As a result, direct hardware implementation of these networks is one promising approach to reducing power consumption and execution time. However, the few hardware implementations of Bayesian networks presented in literature rely on deterministic CMOS devices that are not efficient in representing the inherently stochastic variables in a Bayesian network. This work presents an experimental demonstration of a Bayesian network building block implemented with naturally stochastic spintronic devices. These devices are based on nanomagnets with perpendicular magnetic anisotropy, initialized to their hard axes by the spin orbit torque from a heavy metal under-layer utilizing the giant spin Hall effect, enabling stochastic behavior. We construct an electrically interconnected network of two stochastic devices and manipulate the correlations between their states by changing connection weights and biases. By mapping given conditional probability tables to the circuit hardware, we demonstrate that any two node Bayesian networks can be implemented by our stochastic network. We then present the stochastic simulation of an example case of a four node Bayesian network using our proposed device, with parameters taken from the experiment. We view this work as a first step towards the large scale hardware implementation of Bayesian networks.

cond-mat.mes-hall↗

arXiv2019

A novel compound synapse using probabilistic spin-orbit-torque switching for MTJ based deep neural networks

Analog electronic non-volatile memories mimicking synaptic operations are being explored for the implementation of neuromorphic computing systems. Compound synapses consisting of ensembles of stochastic binary elements are alternatives to analog memory synapses to achieve multilevel memory operation. Among existing binary memory technologies, magnetic tunneling junction (MTJ) based Magnetic Random Access Memory (MRAM) technology has matured to the point of commercialization. More importantly for this work, stochasticity is natural to the MTJ switching physics e.g devices referred as p-bits which mimic binary stochastic neurons. In this article, we experimentally demonstrate a novel compound synapse that uses stochastic spin-orbit torque (SOT) switching of an ensemble of nano-magnets that are located on one shared spin Hall effect (SHE) material channel, i.e. tantalum. By using a properly chosen pulse scheme, we are able to demonstrate linear potentiation and depression in the synapse, as required for many neuromorphic architectures. In addition to this experimental effort, we also performed circuit simulations on an SOT-MRAM based 784*200*10 deep belief network (DBN) consisting of p-bit based neurons and compound synapses. MNIST pattern recognition was used to evaluate the system performance, and our findings indicate that a significant reduction in recognition error rates can be achieved when using our incremental pulse scheme rather than a non-linear potentiation and depression as obtained when employing identical pulses.

physics.app-ph↗

arXiv2019

Demonstration of a strain-mediated magnetoelectric write and read unit in a Co60Fe20B20/ Pb(Mg1/3Nb2/3)0.7Ti0.3O3 heterostructure

Taking advantage of the Magnetoelectric (ME) and its inverse effect, this article demonstrates strain-mediated magnetoelectric write and read operations simultaneously in Co60Fe20B20/ Pb(Mg1/3Nb2/3)0.7Ti0.3O3 heterostructures without using any symmetry breaking magnetic field at room temperature. By applying an external DC-voltage across a (011)-cut PMN-PT substrate, the ferroelectric polarization is re-oriented, which results in an anisotropic in-plane strain that transfers to the CoFeB thin film and changes its magnetic anisotropy Hk. The change in Hk in-turn results in a 90o rotation of the magnetic easy axis for sufficiently high voltages. Simultaneously, the inverse effect is employed to read changes of the magnetic properties. Because the Piezoelectric (PE)/FerroMagnetic (FM) system is fully coupled, the change of magnetization in FM induces an elastic stress in the PE layer, which generates a piezoelectric potential in the system that can be used to readout the magnetic state of the FM layer. Our experimental results are in excellent qualitative agreement with a recently proposed, experimentally benchmarked equivalent circuit model that considers how magnetic properties are electrically controlled in such ME/PE heterostructure and how a back-voltage is generated due to changing magnetic properties in a self-consistent model.

physics.app-ph↗

arXiv2018

Studies of two-dimensional MoS2 on enhancing the electrical performance of ultrathin copper films

Copper nanowires are widely used as on-chip interconnects due to superior conductivity. However, with aggressive Cu interconnect scaling, the diffusive surface scattering of electrons drastically increases the electrical resistivity. In this work, we studied the electrical performance of Cu thin films on different materials. By comparing the thickness dependence of Cu films resistivity on MoS2 and SiO2, we demonstrated that two-dimensional MoS2 can be used to enhance the electrical performance of ultrathin Cu films due to a partial specular surface scattering. By fitting the experimental data with the theoretical Fuchs Sondheimer model, we obtained the specularity parameter at the Cu MoS2 interface in the temperature range 2K to 300K. Furthermore, first principle calculations based on the density functional theory indicates that there are more localized states at the Cu amorphous SiO2 interface than the Cu MoS2 interface which is responsible for the higher resistivity in the Cu SiO2 heterostructure due to more severe electron scattering. Our results suggest that Cu MoS2 hybrid is a promising candidate structure for the future generations of CMOS interconnects.

physics.app-ph↗

arXiv2018

Channel thickness optimization for ultra thin and 2D chemically doped TFETs

2D material based tunnel FETs are among the most promising candidates for low power electronics applications since they offer ultimate gate control and high current drives that are achievable through small tunneling distances during the device operation. The ideal device is characterized by a minimized tunneling distance. However, devices with the thinnest possible body do not necessarily provide the best performance. For example, reducing the channel thickness increases the depletion width in the source which can be a significant part of the total tunneling distance. Hence, it is important to determine the optimum channel thickness for each channel material individually. In this work, we study the optimum channel thickness for three channel materials: WSe$_{2}$, Black Phosphorus (BP), and InAs using full-band self-consistent quantum transport simulations. To identify the ideal channel thickness for each material at a specific doping density, a new analytic model is proposed and benchmarked against the numerical simulations.

physics.comp-ph↗

arXiv2017

Understanding contact gating in Schottky barrier transistors from 2D channels

In this article, a novel two-path model is proposed to quantitatively explain sub-threshold characteristics of back-gated Schottky barrier FETs (SB-FETs) from 2D channel materials. The model integrates the 'conventional' model for SB-FETs with the phenomenon of contact gating - an effect that significantly affects the carrier injection from the source electrode in back-gated field effect transistors. The two-path model is validated by a careful comparison with experimental characteristics obtained from a large number of back-gated WSe2 devices with various channel thicknesses. Our findings are believed to be of critical importance for the quantitative analysis of many three-terminal devices with ultrathin body channels.

cond-mat.mes-hall↗