arXiv subjects

Lance Fernandes

Publications and source records attributed to Lance Fernandes.

5 recordsLinked to original sources

arXiv2026

Thermal Processing Limits in Oxide-Channel Ferroelectric Field Effect Transistors

In this work, we report a systematic study of the impact of high-temperature post-capping thermal annealing on the memory characteristics of Oxide-semiconductor channel ferroelectric field-effect transistors (OS-FeFETs). Using an identical engineered ferroelectric gate stack 8nm Hf0.5Zr0.5O2 (HZO) / 3 nm Al2O3 / 8 nm HZO (8/3/8) and a hybrid capping layer (3 nm HfO2 + 3 nm Al2O3), 10 percent Ga doped InO (IGO) channel and 4 percent W doped InO (IWO) channel FeFETs remain functional after annealing at temperatures up to 650 C for durations of up to 30 min and 10 min, respectively; further annealing results in irreversible loss of conduction and device failure. Detailed electrical analysis reveals that the MW enhancement originates from a preferential positive shift in the erased-state threshold voltage, while the programmed-state threshold voltage remains comparatively stable. Grazing-incidence X-ray diffraction measurements further indicate structural evolution in the IWO and IGO oxide channels with increasing annealing temperature, supporting the observed electrical trends.

cond-mat.mtrl-sci↗

arXiv2026

ALD Oxidant as A Tuning Knob for Memory Window Expansion in Ferroelectric FETs for Vertical NAND Applications

Dielectric inserts are widely used to expand the memory window (MW) in ferroelectric FETs (FeFETs) for vertical NAND applications, with prior efforts focused primarily on material selection and stack positioning. Here, we demonstrate that the ALD oxidant used for the Al2O3 interlayer serves as a process-level tuning knob for MW engineering. H2O-grown Al2O3 yields a significantly larger MW (7-8 V) compared to O3 (4 V) for both gate-injection (12/3) and tunnel dielectric (8/3/8) configurations. While the tunnel dielectric (8/3/8) stack maintains robust retention up to 1e4s at 125C despite the larger MW, the gate-injection (12/3) configuration exhibits pronounced retention degradation for the H2O case. The enhanced MW is attributed to higher interlayer leakage associated with H2O-based ALD. These results establish oxidant choice as a key process parameter for co-optimizing MW and retention in ferroelectric NAND technologies.

cond-mat.mtrl-sci↗

arXiv2025

Hf/Zr Superlattice-Based High-\k{appa} Gate Dielectrics with Dipole Layer Engineering for Advanced CMOS

Advanced logic transistors require gate dielectrics that achieve sub-nanometer equivalent oxide thickness (EOT), suppress leakage, and satisfy three key requirements: (i) compatibility with RMG-like high-temperature processing, (ii) sufficient Vth tunability for multi-Vth design, and (iii) high device reliability. However, meeting all of these requirements simultaneously has been difficult with conventional high-k systems. In this work, we demonstrate that Hf/Zr-based gate stacks quantitatively satisfy these conditions. After a 700 C N2 anneal, the HZH superlattice achieves an EOT of 7.3 A, lower than conventional HfO2-only stacks (8.5 A) while maintaining comparable leakage. Embedding a 3 A Al2O3 dipole within an HfO2/ZrO2/HfO2 superlattice (HZHA) breaks the conventional dipole trade-off, achieving an EOT of 8.4 A, lower than the 9.0 A of a standard HfO2/Al2O3 stack, while providing a flatband voltage shift greater than 200 mV, thereby enabling multi-Vth tuning without compromising scaling. Furthermore, under -2 V negative-bias temperature stress at 125 C for 100 s, HZHA and HA exhibit comparable flatband voltage drifts of 87 mV and 97 mV, respectively, confirming that strong Vth tunability and sub-nanometer EOT can be achieved without compromising stability. In addition to these quantitative advances, this study reveals previously unreported physical insights into dipole behavior and interfacial diffusion in ultrathin Hf/Zr multilayers. These results establish HZHA as an RMG-compatible, Vth-tunable, low-EOT dielectric platform capable of supporting logic scaling beyond the 1 nm frontier.

cond-mat.mes-hall↗

arXiv2025

A Dual-Memory Ferroelectric Transistor Emulating Synaptic Metaplasticity for High-Speed Reservoir Computing

The exponential growth of edge artificial intelligence demands material-focused solutions to overcome energy consumption and latency limitations when processing real-time temporal data. Physical reservoir computing (PRC) offers an energy-efficient paradigm but faces challenges due to limited device scalability and reconfigurability. Additionally, reservoir and readout layers require memory of different timescales, short-term and long-term respectively - a material challenge hindering CMOS-compatible implementations. This work demonstrates a CMOS-compatible ferroelectric transistor using hafnium-zirconium-oxide (HZO) and silicon, enabling dual-memory operation. This system exhibits non-volatile long-term memory (LTM) from ferroelectric HZO polarization and volatile short-term memory (STM) from engineered non-quasi-static (NQS) channel-charge relaxation driven by gate-source/drain overlap capacitance. Ferroelectric polarization acts as non-volatile programming of volatile dynamics: by modulating threshold voltage, the ferroelectric state deterministically switches the NQS time constant and computational behavior between paired-pulse facilitation (PPF) and depression (PPD). This establishes a generalizable material-design principle applicable to diverse ferroelectric-semiconductor heterostructures, extending beyond silicon to oxide semiconductors and heterogeneously-integrated systems. The device solves second-order nonlinear tasks with 3.69 x 10^-3 normalized error using only 16 reservoir states - ~5x reduction - achieving 20 us response time (~1000x faster) and 1.5 x 10^-7 J energy consumption, providing an immediately manufacturable pathway for neuromorphic hardware and energy-efficient edge intelligence.

cond-mat.other↗

arXiv2025

FeNOMS: Enhancing Open Modification Spectral Library Search with In-Storage Processing on Ferroelectric NAND (FeNAND) Flash

The rapid expansion of mass spectrometry (MS) data, now exceeding hundreds of terabytes, poses significant challenges for efficient, large-scale library search - a critical component for drug discovery. Traditional processors struggle to handle this data volume efficiently, making in-storage computing (ISP) a promising alternative. This work introduces an ISP architecture leveraging a 3D Ferroelectric NAND (FeNAND) structure, providing significantly higher density, faster speeds, and lower voltage requirements compared to traditional NAND flash. Despite its superior density, the NAND structure has not been widely utilized in ISP applications due to limited throughput associated with row-by-row reads from serially connected cells. To overcome these limitations, we integrate hyperdimensional computing (HDC), a brain-inspired paradigm that enables highly parallel processing with simple operations and strong error tolerance. By combining HDC with the proposed dual-bound approximate matching (D-BAM) distance metric, tailored to the FeNAND structure, we parallelize vector computations to enable efficient MS spectral library search, achieving 43x speedup and 21x higher energy efficiency over state-of-the-art 3D NAND methods, while maintaining comparable accuracy.

cs.AR↗