arXiv subjects

Laura Bégon-Lours

Publications and source records attributed to Laura Bégon-Lours.

12 recordsLinked to original sources

arXiv2026

20 ps Non-Destructive Read and 1 ns Write Operations at <5 V in Ferroelectric HfO2/ZrO2 Non-Volatile Memories

Achieving low-voltage, nanosecond multi-level programming and non-destructive read-out of ferroelectric non-volatile memories (NVM) is critical for analog in-memory computing architectures relying on ferroelectric capacitive devices (FeCap). We integrate HfO2/ZrO2 ferroelectric nanolayers concurrently in the BEOL of CMOS and on SiO2/Si, achieving nanosecond multilevel switching with programming voltages below 5 V. Partial ferroelectric switching enhances FeCap endurance above 1011 cycles, leading to MemCapacitance (MC) states with non-destructive read-out and 10-year retention. However, experiments reveal the collapse of the MC window for read frequencies above 1 MHz. To overcome this speed limit, we introduce a novel, non-destructive readout methodology. Using electrical pulses with widths down to 20 ps, below the RC time constant of the FeCaps, we enable measurement of the polarization-dependent leakage current, providing ultrafast and non-destructive read operations at only 14 fJ.

physics.app-ph↗

arXiv2026

Personalized Spiking Neural Networks with Ferroelectric Synapses for EEG Signal Processing

Electroencephalography (EEG)-based brain-computer interfaces (BCIs) are strongly affected by non-stationary neural signals that vary across sessions and individuals, limiting the generalization of subject-agnostic models and motivating adaptive and personalized learning on resource-constrained platforms. Programmable memristive hardware offers a promising substrate for such post-deployment adaptation; however, practical realization is challenged by limited weight resolution, device variability, nonlinear programming dynamics, and finite device endurance. In this work, we show that spiking neural networks (SNNs) can be deployed on ferroelectric memristive synaptic devices for adaptive EEG-based motor imagery decoding under realistic device constraints, achieving classification performance comparable to software-based SNNs. We fabricate, characterize, and model the weight update in ferroelectric synapses. We then evaluate the deployment of convolutional-recurrent SNN architecture using two strategies. First, we adapt to SNNs a mixed precision strategy in which gradient-based updates are accumulated digitally and converted into discrete programming events only when a threshold is exceeded. Additionally, the weight update is device-aware and accounts for the nonlinear, state-dependent programming dynamics. During learning and adaptation, this scheme mitigates possible endurance and energy constraints. Second, we evaluate the transfer of software-trained weights followed by low-overhead on-device re-tuning. We show that, subject-specific transfer learning achieved by retraining only the final network layers improves classification accuracy. These results demonstrate that programmable ferroelectric hardware can support robust, low-overhead adaptation in spiking neural networks, opening a practical path toward personalized neuromorphic processing of neural signals.

cs.NE↗

arXiv2026

Analog Weight Update Rule in Ferroelectric Hafnia, using pico-Joule Programming Pulses

In an effort to compete with the brain's efficiency at processing information, neuromorphic hardware combines artificial synapses and neurons using mixed-signal circuits and emerging memories. In ferroelectric resistive weights, the strength of the synaptic connection between two neurons is stored in the device conductance. During learning, programming pulses are applied to the synaptic weight, which reconfigures the ferroelectric domains and adjusts the conductance. One strategy to lower the energy cost during the training phase is to lower the duration of the programming pulses. However, the latter cannot be shorter than the self-loading time of the resistive weights, limited by intrinsic parasitics in the circuits. In this work, ferroelectric resistive weights are fabricated using a process compatible with CMOS Back-End-Of-Line integration, based on hafnia/zirconia nanolaminates. By laterally scaling the device area under 100 $μ$m$^2$, the self-loading time becomes sufficiently short to enable 20 ns programming, which corresponds to a maximum of 3 picoJoules per pulse. Further, in this work, the weight update rule with 20 ns pulses is experimentally measured not only for different amplitudes but also for different initial conductance states. We find that the final weight is determined by the pulse amplitude, independent of the initial weight value.

cs.ET↗

arXiv2025

Unsupervised local learning based on voltage-dependent synaptic plasticity for resistive and ferroelectric synapses

The deployment of AI on edge computing devices faces significant challenges related to energy consumption and functionality. These devices could greatly benefit from brain-inspired learning mechanisms, allowing for real-time adaptation while using low-power. In-memory computing with nanoscale resistive memories may play a crucial role in enabling the execution of AI workloads on these edge devices. In this study, we introduce voltage-dependent synaptic plasticity (VDSP) as an efficient approach for unsupervised and local learning in memristive synapses based on Hebbian principles. This method enables online learning without requiring complex pulse-shaping circuits typically necessary for spike-timing-dependent plasticity (STDP). We show how VDSP can be advantageously adapted to three types of memristive devices (TiO$_2$, HfO$_2$-based metal-oxide filamentary synapses, and HfZrO$_4$-based ferroelectric tunnel junctions (FTJ)) with disctinctive switching characteristics. System-level simulations of spiking neural networks incorporating these devices were conducted to validate unsupervised learning on MNIST-based pattern recognition tasks, achieving state-of-the-art performance. The results demonstrated over 83% accuracy across all devices using 200 neurons. Additionally, we assessed the impact of device variability, such as switching thresholds and ratios between high and low resistance state levels, and proposed mitigation strategies to enhance robustness.

cs.NE↗

arXiv2025

Energy-convergence trade off for the training of neural networks on bio-inspired hardware

The increasing deployment of wearable sensors and implantable devices is shifting AI processing demands to the extreme edge, necessitating ultra-low power for continuous operation. Inspired by the brain, emerging memristive devices promise to accelerate neural network training by eliminating costly data transfers between compute and memory. Though, balancing performance and energy efficiency remains a challenge. We investigate ferroelectric synaptic devices based on HfO2/ZrO2 superlattices and feed their experimentally measured weight updates into hardware-aware neural network simulations. Across pulse widths from 20 ns to 0.2 ms, shorter pulses lower per-update energy but require more training epochs while still reducing total energy without sacrificing accuracy. Classification accuracy using plain stochastic gradient descent (SGD) is diminished compared to mixed-precision SGD. We analyze the causes and propose a ``symmetry point shifting'' technique, addressing asymmetric updates and restoring accuracy. These results highlight a trade-off among accuracy, convergence speed, and energy use, showing that short-pulse programming with tailored training significantly enhances on-chip learning efficiency.

cs.ET↗

arXiv2025

Electroforming Kinetics in HfOx/Ti RRAM: Mechanisms Behind Compositional and Thermal Engineering

A critical issue affecting filamentary resistive random access memory (RRAM) cells is the requirement of high voltages during electroforming. Reducing the magnitude of these voltages is of significant interest, as it ensures compatibility with Complementary Metal-Oxide-Semiconductor (CMOS) technologies. Previous studies have identified that changing the initial stoichiometry of the switching layer and/or implementing thermal engineering approaches has an influence over the electroforming voltage magnitude, but the exact mechanisms remain unclear. Here, we develop an understanding of how these mechanisms work within a standard a-HfO$_x$/Ti RRAM stack through combining atomistic driven-Kinetic Monte Carlo (d-KMC) simulations with experimental data. By performing device-scale simulations at atomistic resolution, we can precisely model the movements of point defects under applied biases in structurally inhomogeneous materials, which allows us to not only capture finite-size effects but also to understand how conductive filaments grow under different electroforming conditions. Doing atomistic simulations at the device-level also enables us to link simulations of the mechanisms behind conductive filament formation with trends in experimental data with the same material stack. We identify a transition from primarily vertical to lateral ion movement dominating the filamentary growth process in sub-stoichiometric oxides, and differentiate the influence of global and local heating on the morphology of the formed filaments. These different filamentary structures have implications for the dynamic range exhibited by formed devices in subsequent SET/RESET operations. Overall, our results unify the complex ion dynamics in technologically relevant HfO$_x$/Ti-based stacks, and provide guidelines that can be leveraged when fabricating devices.

cond-mat.mtrl-sci↗

arXiv2024

TEXEL: A neuromorphic processor with on-chip learning for beyond-CMOS device integration

Recent advances in memory technologies, devices and materials have shown great potential for integration into neuromorphic electronic systems. However, a significant gap remains between the development of these materials and the realization of large-scale, fully functional systems. One key challenge is determining which devices and materials are best suited for specific functions and how they can be paired with CMOS circuitry. To address this, we introduce TEXEL, a mixed-signal neuromorphic architecture designed to explore the integration of on-chip learning circuits and novel two- and three-terminal devices. TEXEL serves as an accessible platform to bridge the gap between CMOS-based neuromorphic computation and the latest advancements in emerging devices. In this paper, we demonstrate the readiness of TEXEL for device integration through comprehensive chip measurements and simulations. TEXEL provides a practical system for testing bio-inspired learning algorithms alongside emerging devices, establishing a tangible link between brain-inspired computation and cutting-edge device research.

cs.NE↗

arXiv2023

A BEOL Compatible, 2-Terminals, Ferroelectric Analog Non-Volatile Memory

A Ferroelectric Analog Non-Volatile Memory based on a WOx electrode and ferroelectric HfZrO$_4$ layer is fabricated at a low thermal budget (~375$^\circ$C), enabling BEOL processes and CMOS integration. The devices show suitable properties for integration in crossbar arrays and neural network inference: analog potentiation/depression with constant field or constant pulse width schemes, cycle to cycle and device to device variation <10%, ON/OFF ratio up to 10 and good linearity. The physical mechanisms behind the resistive switching and conduction mechanisms are discussed.

cs.AR↗

arXiv2023

High-Conductance, Ohmic-like HfZrO$_4$ Ferroelectric Memristor

The persistent and switchable polarization of ferroelectric materials based on HfO$_2$-based ferroelectric compounds, compatible with large-scale integration, are attractive synaptic elements for neuromorphic computing. To achieve a record current density of 0.01 A/cm$^2$ (at a read voltage of 80 mV) as well as ideal memristive behavior (linear current-voltage relation and analog resistive switching), devices based on an ultra-thin (2.7 nm thick), polycrystalline HfZrO$_4$ ferroelectric layer are fabricated by Atomic Layer Deposition. The use of a semiconducting oxide interlayer (WO$_{x<3}$) at one of the interfaces, induces an asymmetric energy profile upon ferroelectric polarization reversal and thus the long-term potentiation / depression (conductance increase / decrease) of interest. Moreover, it favors the stable retention of both the low and the high resistive states. Thanks to the low operating voltage (<3.5 V), programming requires less than 10${^-12}$ J for 20 ns long pulses. Remarkably, the memristors show no wake-up or fatigue effect.

cs.AR↗

arXiv2023

A Back-End-Of-Line Compatible, Ferroelectric Analog Non-Volatile Memory

A Ferroelectric Analog Non-Volatile Memory based on a WOx electrode and ferroelectric HfZrO4 layer is fabricated at a low thermal budget (~375C), enabling BEOL processes and CMOS integration. The devices show suitable properties for integration in crossbar arrays and neural network inference: analog potentiation/depression with constant field or constant pulse width schemes, cycle to cycle and device to device variation <10%, ON/OFF ratio up to 10 and good linearity. The physical mechanisms behind the resistive switching and conduction mechanisms are discussed.

cs.AR↗

arXiv2020

A back-end, CMOS compatible ferroelectric Field Effect Transistor for synaptic weights

Neuromorphic computing architectures enable the dense co-location of memory and processing elements within a single circuit. This co-location removes the communication bottleneck of transferring data between separate memory and computing units as in standard von Neuman architectures for data-critical applications including machine learning. The essential building blocks of neuromorphic systems are non-volatile synaptic elements such as memristors. Key memristor properties include a suitable non-volatile resistance range, continuous linear resistance modulation and symmetric switching. In this work, we demonstrate voltage-controlled, symmetric and analog potentiation and depression of a ferroelectric Hf$_{57}$Zr$_{43}$O$_{2}$ (HZO) field effect transistor (FeFET) with good linearity. Our FeFET operates with a low writing energy (fJ) and fast programming time (40 ns). Retention measurements have been done over 4-bits depth with low noise (1%) in the tungsten oxide (WO$_{x}$) read out channel. By adjusting the channel thickness from 15nm to 8nm, the on/off ratio of the FeFET can be engineered from 1% to 200% with an on-resistance ideally >100 kOhm, depending on the channel geometry. The device concept is using earth-abundant materials, and is compatible with a back end of line (BEOL) integration into complementary metal-oxidesemiconductor (CMOS) processes. It has therefore a great potential for the fabrication of high density, large-scale integrated arrays of artificial analog synapses.

cs.ET↗

arXiv2019

Stabilization of phase-pure rhombohedral HfZrO4 in Pulsed Laser Deposited thin films

Controlling the crystalline structure of Hafnium Zirconate and its epitaxial relationship to a semiconducting electrode has a high technological interest, as ferroelectric materials are key ingredients for emerging electronic devices. Using Pulsed Laser Deposition, a phase pure, ultra-thin film of HfZrO4 is grown epitaxially on a GaN (0001) / Si (111) template. Since standard microscopy techniques do not allow to determine with certitude the crystalline structure of the film due to the weak scattering of oxygen, differentiated differential phase contrast (DPC) Scanning Transmission Electron Microscopy is used to allow the direct imaging of oxygen columns in the film. Combined with X-Rays diffraction analysis, the polar nature and rhombohedral R3 symmetry of the film are demonstrated.

cond-mat.mtrl-sci↗