arXiv subjects

Lei Zhao

Publications and source records attributed to Lei Zhao.

At least 217 records · Page 12Linked to original sources

arXiv2019

An 8-Gs/s 12-Bit TIADC System With Real-Time Broadband Mismatch Error Correction

High sampling speed can be achieved using multiple Analog-to-Digital Converters (ADCs) based on the Time-Interleaving A/D Conversion (TIADC) technique. Various types of methods were proposed to correct the mismatch errors among parallel ADC channels in TIADC systems, which would deteriorate the system performance. Traditional correction methods based on digital signal processing have good performance, however often only for input signals limited in a narrow frequency band. In this paper, we present our recent work on design of an 8-Gsps 12-bit TIADC system and implementation of real-time mismatch correction algorithms in FPGA devices, over a broad band of input signal frequencies. Tests were also conducted to evaluate the systems performance, and the results indicate that the Effective Number of Bits (ENOB) is enhanced to be better than 8.5 bits (<800 MHz) and 8 bits from 800 MHz to 1.6 GHz after correction, almost the same with that of the ADC chip employed.

physics.ins-det↗

arXiv2019

Prototype of the Readout Electronics for WCDA in LHAASO

In the Large High Altitude Air Shower Observatory (LHAASO), the Water Cherenkov Detector Array (WCDA) is one of the key parts. The WCDA consists of 3600 Photomultiplier Tubes (PMTs) scattered in a 90000 m2 area, and both high precision time and charge measurements are required over a large dynamic range from 1 to 4000 Photo Electrons (P.E.). To achieve time measurement precision better than 500 ps RMS, high quality clock distribution and automatic phase compensation are needed among the 400 Front End Electronics (FEE) modules. To simplify the readout electronics architecture, clock, data, and commands are transferred simultaneously over 400-meter fibers, while high speed data transfer interface is implemented based on TCP/IP protocol. Design and testing of the readout electronics prototype for WCDA is presented in this paper. Test results indicate that a charge resolution better than 10% RMS @ 1 P.E. and 1% RMS @ 4000 P.E., and a time resolution better than 300 ps RMS are successfully achieved over the whole dynamic range, beyond the application requirement.

physics.ins-det↗

arXiv2019

Precise Clock Synchronization in the Readout Electronics of WCDA in LHAASO

The Water Cherenkov Detector Array (WCDA) is one of the key parts in the Large High Altitude Air Shower Observatory (LHAASO). In the WCDA, 3600 Photomultiplier Tubes (PMTs) and the Front End Electronics (FEEs) are scattered within a 90000 m2 area, while a time measurement resolution better than 0.5 ns is required in the readout electronics. To achieve such time measurement precision, high quality clock distribution and synchronization among the 400 FEEs (each FEE for 9 PMTs readout) is required. To simplify the electronics system architecture, data, commands, and clock are transmitted simultaneously through fibers over a 400-meter distance between FEEs and the Clock and Data Transfer Modules (CDTMs). In this article, we propose a new method based on the White Rabbit (WR) to achieve completely automatic clock phase alignment between different FEEs. The original WR is enhanced to overcome the clock delay fluctuations due to ambient temperature variations. This paper presents the general scheme, the design of prototype electronics, and initial test results. These indicate that a clock synchronization precision better than 50 ps is achieved over 1 km fibers, which is well beyond the application requirement.

physics.ins-det↗

arXiv2019

Bunch-by-bunch Beam Transverse Feedback Electronics Designed for SSRF

Shanghai Synchrotron Radiation Facility (SSRF), is one of the third-generation high-beam current (3.5 GeV) synchrotron light sources. In the storage ring of SSRF, multi-bunch instabilities would increase beam emittance and energy spread, which degrade beam quality and even cause beam loss. To address the above issues, a Transverse Feedback System is indispensable for SSRF, in which the key component is the bunch-by-bunch transverse feedback electronics. The whole feedback system consists of five main parts: Beam Position Monitor (BPM), RF front-end, signal processor, RF amplifier, and vertical/horizontal transverse kickers. The dissertation focuses on the signal processor we design, which is the main part of the feedback electronics. We conducted initial testing on the signal processor to evaluate its performance and function. Test results indicate that ENOB of the Analog-to-Digital Conversion circuit is better than 10 bit with 100 MHz input signal, and remains better than 9.5 bit up to 300 MHz, which is good enough for the required 7.9 bit; the frequency response of the whole system also concords well with the simulation results, and the suppression in amplitude response at the critical frequency points is better 35 dB while the uncertainty of phase response is better than 2 degree, all meeting the application requirement.

physics.ins-det↗

arXiv2019

Prototype of a front-end readout ASIC designed for the Water Cherenkov Detector Array in LHAASO

The Large High Altitude Air Shower Observatory is in the R&D phase, in which the Water Cherenkov Detector Array is an important part. The signals of Photo-Multiplier Tubes would vary from single photo electron to 4000 photo electrons, and both high precision charge and time measurement is required. To simplify the signal processing chain, the charge-to-time conversion method is employed. A prototype of the front-end readout ASIC is designed and fabricated in Chartered 0.35 μm CMOS technology, which integrates time disctrimination and converts the input charge information to pulse widths. With Time-to-Digital Converters, both time and charge can be digitized at the same time. We have conducted initial tests on this chip, and the results indicate that a time resolution better than 0.5 ns is achieved over the full dynamic range (1~ 4000 photo electrons, corresponding to 0.75 ~ 3000 pC with the threshold of 0.188 pC); the charge resolution is better than 1% with large input amplitudes (500 ~ 4000 photo electrons), and remains better than 15% with a 1 photo electron input amplitude, which is beyond the application requirement.

physics.ins-det↗

arXiv2019

Research of time discrimination circuits for PMT signal readout over large dynamic range in LHAASO WCDA

In the readout electronics of the Water Cerenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO), both high-resolution charge and time measurement are required over a dynamic range from 1 photoelectron (P.E.) to 4000 P.E. for the PMT signal readout. In this paper, we present our work on the design of time discrimination circuits in LHAASO WCDA, especially on improvement to reduce the circuit dead time. Several approaches were studied through analysis and simulations, and actual circuits were designed and tested in the laboratory to evaluate the performance. Test results indicate that a time resolution better than 500 ps RMS is achieved in the whole large dynamic range, and the circuit dead time is successfully reduced to less than 200 ns.

physics.ins-det↗

arXiv2019

Data and clock transmission interface for the WCDA in LHAASO

The Water Cherenkov Detector Array (WCDA) is one of the major components of the Large High Altitude Air Shower Observatory (LHAASO). In the WCDA, 3600 Photomultiplier Tubes (PMTs) and the Front End Electronics (FEEs) are scattered over a 90000 m2 area, while high precision time measurements (0.5 ns RMS) are required in the readout electronics. To meet this requirement, the clock has to be distributed to the FEEs with high precision. Due to the "triggerless" architecture, high speed data transfer is required based on the TCP/IP protocol. To simplify the readout electronics architecture and be consistent with the whole LHAASO readout electronics, the White Rabbit (WR) switches are used to transfer clock, data, and commands via a single fiber of about 400 meters. In this paper, a prototype of data and clock transmission interface for LHAASO WCDA is developed. The performance tests are conducted and the results indicate that the clock synchronization precision of the data and clock transmission is better than 50 ps. The data transmission throughput can reach 400 Mbps for one FEE board and 180 Mbps for 4 FEE boards sharing one up link port in WR switch, which is better than the requirement of the LHAASO WCDA.

physics.ins-det↗

arXiv2019

Prototype of a transient waveform recording ASIC

The paper presents the design and measurement results of a transient waveform recording ASIC based on the Switched Capacitor Array (SCA) architecture. This 0.18 μm CMOS prototype device contains two channels and each channel employs a SCA of 128 samples deep, a 12-bit Wilkinson ADC and a serial data readout. A series of tests have been conducted and the results indicate that: a full 1 V signal voltage range is available, the input analog bandwidth is approximately 450 MHz and the sampling speed is adjustable from 0.076 to 3.2 Gsps (Gigabit Samples Per Second). For precision waveform timing extraction, careful calibration of timing intervals between samples is conducted to improve the timing resolution of such chips, and the timing precision of this ASIC is proved to be better than 15 ps RMS.

physics.ins-det↗

arXiv2019

Design and testing of a bunch-by-bunch beam position transverse feedback processor

Shanghai Synchrotron Radiation Facility (SSRF) is a 3.5 GeV storage ring with a bunch rate of 499.654 MHz, harmonic number of 720, and circumference of 432 meters. SSRF injection works at 3.5 GeV, where the multi-bunch instabilities limit the maximum stored current. In order to suppress multi-bunch instabilities caused by transverse impedance, a bunch-by-bunch transverse feedback system is indispensable for SSRF. The key component of that system is the bunch-by-bunch transverse feedback electronics. An important task in the electronics is precise time synchronization. In this paper, a novel clock synchronization and precise delay adjustment method based on the PLLs and delay lines are proposed. Test results indicate that the ENOB (Effective Number Of Bits) of the analog-to-digital conversion circuit is better than 9 bits in the input signal frequency range from 100 kHz to 700 MHz, and the closed loop attenuation at the critical frequency points is better than 40 dB. The initial commissioning tests with the beam in SSRF are also conducted, and the results are consistent with the expectations.

physics.ins-det↗

arXiv2019

An overdetermined linear equations-based time calibration method for fast sampling ASICs

A novel time calibration method for waveform sampling application specific integrated circuits (ASICs) based on switched capacitor arrays (SCAs) is proposed in this paper. Precision timing extraction using SCA ASICs has been proved to be a promising technique in many high energy physics experiments. However, such ASICs suffer from irregular sampling intervals caused by process variations. Therefore, careful calibration is required to improve the time resolution of such systems. We evaluated the limitation of a popular method using the proportionality between voltage amplitude and sampling interval of adjacent switched-capacitor cells responding to either a sawtooth wave or a sine wave. The new time calibration method presented here utilizes the relationship between sampling intervals and the known input signal period to establish overdetermined linear equations, and the roots of these equations correspond to the actual sampling intervals. We applied this new method to a pulse timing test with an ASIC designed by our team, and the test results indicate that the new time calibration method is effective.

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arXiv2019

Linear Convergence of Variable Bregman Stochastic Coordinate Descent Method for Nonsmooth Nonconvex Optimization by Level-set Variational Analysis

Large-scale nonconvex and nonsmooth problems have attracted considerable attention in the fields of compress sensing, big data optimization and machine learning. Exploring effective methods is still the main challenge of today's research. Stochastic coordinate descent type methods have been widely used to solve large-scale optimization problems. In this paper, we derive the convergence of variable Bregman stochastic coordinate descent (VBSCD) method for a broad class of nonsmooth and nonconvex optimization problems, i.e., any accumulation of the sequence generated by VBSCD is almost surely a critical point. Moreover, we develop a new variational approach on level sets that aim towards the convergence rate analysis. If the level-set subdifferential error bound holds, we derive a linear rate of convergence for the expected values of the objective function and expected values of random variables generated by VBSCD.

math.OC↗

arXiv2019

Design and performance of a TDC ASIC for the upgrade of the ATLAS Monitored Drift Tube detector

We present the prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for high-luminosity LHC operation. This ASIC is based on a previously submitted demonstrator ASIC designed for timing performance evaluation, and includes all features necessary for the various operation modes, as well as the migration to the TSMC 130 nm CMOS technology. We present the TDC design with the emphasis on added features and performance optimization. Tests of the timing performance demonstrate that this ASIC meets the design specifications. The TDC has a bin size of about 780 ps, and a timing bin variations within 40 ps for all 24 channels with leading and trailing edge digitization, while the power consumption has been limited to 250 mW, corresponding to a consumption of about 5.2 mW per edge measurement.

physics.ins-det↗

arXiv2019

Stochastic Primal-Dual Coordinate Method with Large Step Size for Composite Optimization with Composite Cone-constraints

We introduce a stochastic coordinate extension of the first-order primal-dual method studied by Cohen and Zhu (1984) and Zhao and Zhu (2018) to solve Composite Optimization with Composite Cone-constraints (COCC). In this method, we randomly choose a block of variables based on the uniform distribution. The linearization and Bregman-like function (core function) to that randomly selected block allow us to get simple parallel primal-dual decomposition for COCC. We obtain almost surely convergence and O(1/t) expected convergence rate in this work. The high probability complexity bound is also derived in this paper.

math.OC↗

arXiv2018

Mismatch error correction for time interleaved analog-to-digital converter over a wide frequency range

High-speed high-resolution Analog-to-Digital Conversion is the key part for waveform digitization in physics experiments and many other domains. This paper presents a new fully digital correction of mismatch errors among the channels in Time Interleaved Analog-to-Digital Converter (TIADC) systems. We focus on correction with wide-band input signal, which means that we can correct the mismatch errors for any frequency point in a broad band with only one set of filter coefficients. Studies were also made to show how to apply the correction algorithm beyond the base band, i.e. other Nyquist zones in the under-sampling situation. Structure of the correction algorithm is presented in this paper, as well as simulation results. To evaluate the correction performance, we actually conducted a series of tests with two TIADC systems. The results indicate that the performance of both two TIADC systems can be greatly improved by correction, and the Effective Number Of Bits (ENOB) is successfully improved to be better than 9.5 bits and 5.5 bits for an input signal up to the bandwidth (-3dB) range in the 1.6-Gsps 14-bit and the 10-Gsps 8-bit TIADC systems, respectively. Tests were also conducted for input signal frequencies in the second Nyquist zone, which shows that the correction algorithms also work well as expected.

eess.SP↗

arXiv2018

GLStyleNet: Higher Quality Style Transfer Combining Global and Local Pyramid Features

Recent studies using deep neural networks have shown remarkable success in style transfer especially for artistic and photo-realistic images. However, the approaches using global feature correlations fail to capture small, intricate textures and maintain correct texture scales of the artworks, and the approaches based on local patches are defective on global effect. In this paper, we present a novel feature pyramid fusion neural network, dubbed GLStyleNet, which sufficiently takes into consideration multi-scale and multi-level pyramid features by best aggregating layers across a VGG network, and performs style transfer hierarchically with multiple losses of different scales. Our proposed method retains high-frequency pixel information and low frequency construct information of images from two aspects: loss function constraint and feature fusion. Our approach is not only flexible to adjust the trade-off between content and style, but also controllable between global and local. Compared to state-of-the-art methods, our method can transfer not just large-scale, obvious style cues but also subtle, exquisite ones, and dramatically improves the quality of style transfer. We demonstrate the effectiveness of our approach on portrait style transfer, artistic style transfer, photo-realistic style transfer and Chinese ancient painting style transfer tasks. Experimental results indicate that our unified approach improves image style transfer quality over previous state-of-the-art methods, while also accelerating the whole process in a certain extent. Our code is available at https://github.com/EndyWon/GLStyleNet.

cs.CV↗

arXiv2018

A Design of FPGA Based Small Animal PET Real Time Digital Signal Processing and Correction Logic

Small animal Positron Emission Tomography (PET) is dedicated to small animal imaging. Animals used in experiments, such as rats and monkeys, are often much smaller than human bodies, which requires higher position and energy precision of the PET imaging system. Besides, Flexibility, high efficiency are also the major demands of a practical PET system. These requires a high-quality analog front-end and a digital signal processing logic with high efficiency and compatibility of multiple data processing modes. The digital signal processing logic of the small animal PET system presented in this paper implements 32-channel signal processing in a single Xilinx Artix-7 family of Field-Programmable Gate Array (FPGA). The logic is designed to support three online modes which are regular package mode, flood map and energy spectrum histogram. Several functions are integrated, including two-dimensional (2D) raw position calculation, crystal identification, events filtering, etc. Besides, a series of online corrections are also integrated, such as photon peak correction to 511 keV and timing offset correction with crystal granularity. A Gigabit Ethernet interface is utilized for data transfer, Look-Up Tables (LUTs) configuration and commands issuing. The pipe-line logic processes the signals at 125 MHz with a rate of 1,000,000 events/s. A series of initial tests are conducted. The results indicate that the digital processing logic achieves the expectations.

eess.SP↗

arXiv2018

A New All-Digital Background Calibration Technique for Time-Interleaved ADC Using First Order Approximation FIR Filters

This paper describes a new all-digital technique for calibration of the mismatches in time-interleaved analog-to-digital converters (TIADCs) to reduce the circuit area. The proposed technique gives the first order approximation of the gain mismatches and sample-time mismatches, and employs first order approximation FIR filter banks to calibrate the sampled signal, which do not need large number of FIR taps. In the case of a two-channel 12-bit TIADC, the proposed technique improves SINAD of simulated data from 45dB to 69dB, and improves SINAD of measured data from 47dB to 53dB, while the number of FIR taps is only 30. In the case of slight mismatches, 24-bit FIR coefficient is sufficient to correct 12-bit signals, which makes it easy to implement this technique in hardware. In addition, this technique is not limited by the number of sub-ADC channels and can be calculated in parallel in hardware, these features enable this technique to be versatile and capable of real-time calibration.

eess.SP↗

arXiv2018

Testing of Front-End Readout Prototype ASICs Designed for WCDA in LHAASO

The water Cherenkov detector array (WCDA) is one of the key detectors in the large high altitude air shower observatory (LHAASO), which is proposed for very high gamma ray source survey. In WCDA, there are more than 3000 photomultiplier tubes (PMTs) scattered under water in an area of 80000 m2. As for the WCDA readout electronics, both high precision time and charge measurement is required over a large dynamic range from 1 photon electron (P.E.) to 4000 P.E. To reduce the electronics complexity and improve the system reliability, a readout scheme based on application specific integrated circuits (ASICs) is proposed. Two prototype ASICs were designed and tested. The first ASIC integrates amplification and shaping circuits for charge measurement and discrimination circuits used for time measurement. The shaped signal is further fed to the second ADC ASIC, while the output signal from the discriminator is digitized by the FPGA-based time-to-digital converter (TDC). Test results indicate that time resolution is better than 250 ps RMS, and the charge resolution is better than 10% at 1 P.E., and 1% at 4000 P.E. which meets the requirements of the LHAASO WCDA.

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