arXiv subjects

Magnus Mager

Publications and source records attributed to Magnus Mager.

11 recordsLinked to original sources

arXiv2026

Charge sharing and alignment performance of bent ALPIDEs measured with low-energy protons

The upgrade of the ALICE experiments Inner Tracking System (ITS3) aims to replace its innermost detection layers with bent wafer-scale CMOS MAPS sensors. This study examines the performance of ALPIDE chips, currently used in the ALICE ITS2, when operated in a bent configuration under realistic experimental conditions. Proton beams with energies of 80 MeV, 120 MeV and 200 MeV were used to study proton-proton elastic scattering on a polypropylene fiber target reconstructed using two opposing arms of trackers with sensors bent to radii of 18 mm, 24 mm and 30 mm. The measured low-momentum protons provided a testbed for investigating clustering behavior in high-energy loss events, where no significant impact of bending was observed on cluster size. Additionally, alignment strategies for bent detectors were evaluated using the distance of closest approach (DCA) and opening angle between scattered proton tracks as benchmarks. The achieved resolution matches expectations from simulations, confirming the suitability of bent MAPS sensors for future high-energy and nuclear physics applications.

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arXiv2026

A Novel Approach for Fault Detection and Failure Analysis of CMOS Copper Metal Stacks

For the Inner Tracking System 3 (ITS3) upgrade, the ALICE experiment at CERN requires monolithic active pixel sensors of dimensions up to 97~mm$\,\times\,$266~mm, occupying a large fraction of a 300 mm wafer. To manufacture such a wafer-scale device, larger than the single design reticle size, stitching is employed. The MOnolithic Stitched Sensor (MOSS) is a prototype silicon pixel sensor of 14~mm$\,\times\,$259~mm size with the primary goal of understanding the stitching technique and yield. Given the large size, high yield is paramount for the ITS3 sensors, and an in-depth yield characterization was performed on these MOSS sensors. In a collaborative effort, the foundry adapted the metal stack to the requirements of the project, but recurrent fault signatures were discovered with various frequencies across all 20 wafers tested, and correlated through dedicated measurements and analyses. Following these findings, the foundry implemented a mitigation strategy to avoid the issue in the future. This article does not describe process details but concentrates on the measurements and analysis method.

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arXiv2025

Influence of Radiation and AC Coupling on Time Performance of Analog Pixels Test Structures in 65 nm CMOS technology

Monolithic Active Pixel Sensors (MAPS) in advanced CMOS imaging technologies are key to next-generation tracking systems for high-energy physics, where radiation hardness and precise vertex reconstruction are essential. As part of the ALICE ITS3 R&D program in synergy with the CERN R&D, we evaluated the performance of the Analog Pixel Test Structures (APTS) fabricated in the TPSCo 65 nm CMOS imaging process. The prototypes employ 10 um pitch pixels with a fast operational amplifier-based buffering stage at the output, enabling direct characterization of intrinsic sensor response. Beam tests with minimum ionizing particles assessed the timing and charge collection of DC- and AC-coupled designs, including devices exposed to 10^14 NIEL and 10^15 NIEL non ioninsing energy loss. DC-coupled sensors demonstrated stable performance, maintaining time resolution lower than 70 ps and >99% detection efficiency up to 10^15 NIEL. AC-coupled sensors demonstrated a wide operational margin, with efficiencies above 99% for clusterization thresholds below 150 electrons. Even though the AC coupling allows higher reverse bias than DC-coupled sensors, the reduced signal amplitude lowers the signal-to-noise ratio, increasing the jitter contribution. At high reverse bias, the AC-coupled sensors achieve time resolutions comparable to the DC-coupled version, demonstrating the viability of both approaches. These results also suggest that combining the low capacitance of DC-coupled designs with the high-bias capability of AC coupling could further enhance time resolution. These results confirm the suitability of 65 nm MAPS for future collider detectors requiring high radiation tolerance, efficiency, and timing precision.

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arXiv2025

Characterisation of the first wafer-scale prototype for the ALICE ITS3 upgrade: the monolithic stitched sensor (MOSS)

This paper presents the characterisation and testing of the first wafer-scale monolithic stitched sensor (MOSS) prototype developed for the ALICE ITS3 upgrade that is to be installed during the LHC Long Shutdown 3 (2026-2030). The MOSS chip design is driven by the truly cylindrical detector geometry that imposes that each layer is built out of two wafer-sized, bent silicon chips. The stitching technique is employed to fabricate sensors with dimensions of 1.4 $\times$ 25.9 cm, thinned to 50 $\mu$m. The chip architecture, in-pixel front-end, laboratory and in-beam characterisation, susceptibility to single-event effects, and series testing are discussed. The testing campaign validates the design of a wafer-scale stitched sensor and the performance of the pixel matrix to be within the ITS3 requirements. The MOSS chip demonstrates the feasibility of the ITS3 detector concept and provides insights for further optimisation and development.

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arXiv2025

Yield, noise and timing studies of ALICE ITS3 stitched sensor test structures: the MOST

In the LHC long shutdown 3, the ALICE experiment upgrades the inner layers of its Inner Tracker System with three layers of wafer-scale stitched sensors bent around the beam pipe. Two stitched sensor evaluation structures, the MOnolithic Stitched Sensor (MOSS) and MOnolithic Stitched Sensor with Timing (MOST) allow the study of yield dependence on circuit density, power supply segmentation, stitching demonstration for power and data transmission, performance dependence on reverse bias, charge collection performance, parameter uniformity across the chip, and performance of wafer-scale data transmission. The MOST measures 25.9 cm x 0.25 cm, has more than 900,000 pixels of 18x18 $\mu$m$^2$ and emphasizes the validation of pixel circuitry with maximum density, together with a high number of power domains separated by switches allowing to disconnect faulty circuits. It employs 1 Gb/s 26 cm long data transmission using asynchronous, data-driven readout. This readout preserves information on pixel address, time of arrival and time over threshold. In the MOSS, by contrast, regions with different in-pixel densities are implemented to study yield dependence and are read synchronously. MOST test results validated the concept of power domain switching and the data transmission over 26 cm stitched lines which are to be employed on the full-size, full-functionality ITS3 prototype sensor, MOSAIX. Jitter of this transmission is still under study. This proceeding summarizes the performance of the stitched sensor test structures with emphasis on the MOST.

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arXiv2025

Further Characterisation of Digital Pixel Test Structures Implemented in a 65 nm CMOS Process

The next generation of MAPS for future tracking detectors will have to meet stringent requirements placed on them. One such detector is the ALICE ITS3 that aims to be very light at 0.07% X/X$_{0}$ per layer and have a low power consumption in the active area of 40 mW/cm$^{2}$ by implementing wafer-scale MAPS bent into cylindrical half layers. To address these challenging requirements, the ALICE ITS3 project, in conjunction with the CERN EP R&D on monolithic pixel sensors, proposed the Tower Partners Semiconductor Co. 65 nm CMOS process as the starting point for the sensor. After the initial results confirmed the detection efficiency and radiation hardness, the choice of the technology was solidified by demonstrating the feasibility of operating MAPS in low-power consumption regimes, < 50 mW/cm$^{2}$, while maintaining high-quality performance. This was shown through a detailed characterisation of the Digital Pixel Test Structure (DPTS) prototype exposed to X-rays and ionising beams, and the results are presented in this article. Additionally, the sensor was further investigated through studies of the fake-hit rate, the linearity of the front-end in the range 1.7-28 keV, the performance after ionising irradiation, and the detection efficiency of inclined tracks in the range 0-45$^\circ$.

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arXiv2025

Detection efficiency and spatial resolution of Monolithic Active Pixel Sensors bent to different radii

Bent monolithic active pixel sensors are the basis for the planned fully cylindrical ultra low material budget tracking detector ITS3 of the ALICE experiment. This paper presents results from testbeam campaigns using high-energy particles to verify the performance of 50 um thick bent ALPIDE chips in terms of efficiency and spatial resolution. The sensors were bent to radii of 18, 24 and 30 mm, slightly smaller than the foreseen bending radii of the future ALICE ITS3 layers. An efficiency larger than $99.9\%$ and a spatial resolution of approximately 5 um, in line with the nominal operation of flat ALPIDE sensors, is obtained at nominal operating conditions. These values are found to be independent of the bending radius and thus constitute an additional milestone in the demonstration of the feasibility of the planned ITS3 detector. In addition, a special geometry in which the beam particles graze the chip and traverse it laterally over distances of up to 3 mm is investigated.

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arXiv2024

Characterisation of analogue MAPS produced in the 65 nm TPSCo process

Within the context of the ALICE ITS3 collaboration, a set of MAPS small-scale test structures were developed using the 65 nm TPSCo CMOS imaging process with the upgrade of the ALICE inner tracking system as its primary focus. One such sensor, the Circuit Exploratoire 65 nm (CE-65), and its evolution the CE-65v2, were developed to explore charge collection properties for varying configurations including collection layer process (standard, blanket, modified with gap), pixel pitch (15, 18, \SI{22.5}{\micro\meter}), and pixel geometry (square vs hexagonal/staggered). In this work the characterisation of the CE-65v2 chip, based on $^{55}$Fe lab measurements and test beams at CERN SPS, is presented. Matrix gain uniformity up to the $\mathcal{O}$(5\%) level was demonstrated for all considered chip configurations. The CE-65v2 chip achieves a spatial resolution of under \SI{2}{\micro\meter} during beam tests. Process modifications allowing for faster charge collection and less charge sharing result in decreased spatial resolution, but a considerably wider range of operation, with both the \SI{15}{\micro\meter} and \SI{22.5}{\micro\meter} chips achieving over 99\% efficiency up to a $\sim$180 e$^{-}$ seed threshold. The results serve to validate the 65 nm TPSCo CMOS process, as well as to motivate design choices in future particle detection experiments.

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arXiv2024

Time performance of Analog Pixel Test Structures with in-chip operational amplifier implemented in 65 nm CMOS imaging process

In the context of the CERN EP R&D on monolithic sensors and the ALICE ITS3 upgrade, the Tower Partners Semiconductor Co (TPSCo) 65 nm process has been qualified for use in high energy physics, and adopted for the ALICE ITS3 upgrade. An Analog Pixel Test Structure (APTS) featuring fast per pixel operational-amplifier-based buffering for a small matrix of four by four pixels, with a sensor with a small collection electrode and a very non-uniform electric field, was designed to allow detailed characterization of the pixel performance in this technology. Several variants of this chip with different pixel designs have been characterized with a (120 GeV/$c$) positive hadron beam. This result indicates that the APTS-OA prototype variants with the best performance achieve a time resolution of 63 ps with a detection efficiency exceeding 99% and a spatial resolution of 2 $\mu$m, highlighting the potential of TPSCo 65nm CMOS imaging technology for high-energy physics and other fields requiring precise time measurement, high detection efficiency, and excellent spatial resolution.

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arXiv2024

Characterisation of analogue Monolithic Active Pixel Sensor test structures implemented in a 65 nm CMOS imaging process

Analogue test structures were fabricated using the Tower Partners Semiconductor Co. CMOS 65 nm ISC process. The purpose was to characterise and qualify this process and to optimise the sensor for the next generation of Monolithic Active Pixels Sensors for high-energy physics. The technology was explored in several variants which differed by: doping levels, pixel geometries and pixel pitches (10-25 $\mu$m). These variants have been tested following exposure to varying levels of irradiation up to 3 MGy and $10^{16}$ 1 MeV n$_\text{eq}$ cm$^{-2}$. Here the results from prototypes that feature direct analogue output of a 4$\times$4 pixel matrix are reported, allowing the systematic and detailed study of charge collection properties. Measurements were taken both using $^{55}$Fe X-ray sources and in beam tests using minimum ionizing particles. The results not only demonstrate the feasibility of using this technology for particle detection but also serve as a reference for future applications and optimisations.

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arXiv2022

Digital Pixel Test Structures implemented in a 65 nm CMOS process

The ALICE ITS3 (Inner Tracking System 3) upgrade project and the CERN EP R&D on monolithic pixel sensors are investigating the feasibility of the Tower Partners Semiconductor Co. 65 nm process for use in the next generation of vertex detectors. The ITS3 aims to employ wafer-scale Monolithic Active Pixel Sensors thinned down to 20 to 40 um and bent to form truly cylindrical half barrels. Among the first critical steps towards the realisation of this detector is to validate the sensor technology through extensive characterisation both in the laboratory and with in-beam measurements. The Digital Pixel Test Structure (DPTS) is one of the prototypes produced in the first sensor submission in this technology and has undergone a systematic measurement campaign whose details are presented in this article. The results confirm the goals of detection efficiency and non-ionising and ionising radiation hardness up to the expected levels for ALICE ITS3 and also demonstrate operation at +20 C and a detection efficiency of 99% for a DPTS irradiated with a dose of $10^{15}$ 1 MeV n$_{\mathrm{eq}}/$cm$^2$. Furthermore, spatial, timing and energy resolutions were measured at various settings and irradiation levels.

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