arXiv subjects

Mario Saggio

Publications and source records attributed to Mario Saggio.

6 recordsLinked to original sources

arXiv2024

Impact of the NO annealing duration on the SiO2/4H-SiC interface properties in lateral MOSFETs: the energetic profile of the near-interface-oxide traps

In this work, the effects of the duration of the post deposition annealing (PDA) in nitric oxide (NO) on the properties of SiO2/4H-SiC interfaces in n-channel lateral MOSFETs are investigated, with a special focus on the modifications of the energy profile of near-interface-oxide traps (NIOTs). For this purpose, the electrical characteristics of lateral MOSFETs were studied in strong inversion conditions, monitoring the threshold voltage variations due to charge trapping effects. To determine the energetic position of the NIOTs with respect of the SiO2 conduction band edge, the Fermi level position in the insulating layer was evaluated by TCAD simulations of the band diagrams. PDAs of the gate oxide of different duration resulted into similar shape of the energetic profile of the traps inside the insulator with respect of the SiO2 conduction band edge, but with different magnitude. Finally, the effective decrease of the insulator traps is demonstrated despite a saturation of the interface state density under prolonged PDAs and in particular the charge trapped at the NIOTs is reduced from 1-2 x 1011 cm-2 down to 3 x 1011 cm-2 varying the PDA duration from 10 up to 120 min in NO at 1175 degree C.

cond-mat.mtrl-sci↗

arXiv2024

Complementary two dimensional carrier profiles of 4H-SiC MOSFETs by Scanning Spreading Resistance Microscopy and Scanning Capacitance Microscopy

This paper reports the results presented in an invited poster during the International Conference on Silicon Carbide and Related Materials (ICSCRM) 2023 held in Sorrento, Italy. The suitability of scanning probe methods based on atomic force microscopy (AFM) measurements is explored to investigate with high spatial resolution the elementary cell of 4H-SiC power MOSFETs. The two-dimensional (2D) cross-sectional maps demonstrated a high spatial resolution of about 5 nm using the SSRM capabilities. Furthermore, the SCM capabilities enabled visualizing the fluctuations of charge carrier concentration across the different parts of the MOSFETs elementary cell.

physics.app-ph↗

arXiv2020

Interfacial electrical and chemical properties of deposited SiO2 layers in lateral implanted 4H-SiC MOSFETs subjected to different nitridations

In this paper, SiO2 layers deposited on 4H-SiC and subjected to different post deposition annealing (PDA) in NO and N2O were studied to identify the key factors influencing the channel mobility and threshold voltage stability in 4H-SiC MOSFETs. In particular, PDA in NO gave a higher channel mobility (55 cm2V-1s-1) than PDA in N2O (20 cm2V-1s-1), and the subthreshold behavior of the devices confirmed a lower total amount of interface states for the NO case. This latter could be also deduced from the behavior of the capacitance-voltage characteristics of 4H-SiC MOSFETs measured in gate controlled diode configuration. On the other hand, cyclic gate bias stress measurements allowed to separate the contributions of interface states (Nit) both on the upper and bottom parts of the 4H-SiC band gap and near interface oxide traps (NIOTs) in the two oxides. In particular, it was found that NO annealing reduced the total density of charges trapped at the interface states down to 3 x 1011 cm- 2 and those trapped inside the oxide down to 1 x 1011 cm-2. Electron energy loss spectroscopy demonstrated that the reduction of these traps in the NO annealed sample is due to the lower amounts of sub-stoichiometric silicon oxide (~ 1nm) and carbon-related defects (< 1nm) at the interface, respectively. This correlation represents a further step in the comprehension of the physics of the SiO2/4H-SiC interface explaining the mobility and threshold voltage behavior of 4H-SiC MOSFETs.

cond-mat.mtrl-sci↗

arXiv2020

Electrical properties of inhomogeneous tungsten carbide Schottky barrier on 4H-SiC

In this paper, the electrical behavior of tungsten carbide (WC) Schottky barrier on 4H-SiC was investigated. First, a statistical current-voltage (I-V) analysis in forward bias, performed on a set of equivalent diodes, showed a symmetric Gaussian-like distribution of the barrier heights after annealing at 700{\deg}C, where a low Schottky barrier height ($\Phi$B=1.05 eV) and an ideality factor n=1.06 were measured. The low value of the barrier height makes such a WC contact an interesting candidate to reduce the conduction losses in 4H-SiC Schottky diodes. A deeper characterization has been carried out, by monitoring the temperature dependence of the I-V characteristics and the behavior of the relevant parameters $\Phi$B and n. The increase of the barrier height and decrease of the ideality factor with increasing temperature indicated a lateral inhomogeneity of the WC/4H-SiC Schottky contact, which was described by invoking the Tung's model. Interestingly, the temperature dependence of the leakage current under reverse bias could be described by considering in the thermionic field emission model the temperature dependent barrier height related to the inhomogeneity. These results can be useful to predict the behavior of WC/4H-SiC Schottky diodes under operative conditions.

physics.app-ph↗

arXiv2020

Identification of two trapping mechanisms responsible of the threshold voltage variation in SiO$_2$/4H-SiC MOSFETs

A non-relaxing method based on cyclic gate bias stress is used to probe the interface or near-interface traps in the SiO$_2$/4H-SiC system over the whole 4H-SiC band gap. The temperature dependent instability of the threshold voltage in lateral MOSFETs is investigated and two separated trapping mechanisms were found. One mechanism is nearly temperature independent and it is correlated to the presence of near interface oxide traps that are trapped via tunneling from the semiconductor. The second mechanism, having an activation energy of 0.1 eV, has been correlated to the presence of intrinsic defects at the SiO$_2$/4H-SiC interface.

physics.app-ph↗

arXiv2020

Electron trapping at SiO2/4H-SiC interface probed by transient capacitance measurements and atomic resolution chemical analysis

Studying the electrical and structural properties of the interface of the gate oxide (SiO2) with silicon carbide (4H-SiC) is a fundamental topic, with important implications for understanding and optimizing the performances of metal-oxide-semiconductor field effect transistor (MOSFETs). In this paper, near interface oxide traps (NIOTs) in lateral 4H-SiC MOSFETs were investigated combining transient gate capacitance measurements (C-t) and state of the art scanning transmission electron microscopy in electron energy loss spectroscopy (STEM-EELS) with sub-nm resolution. The C-t measurements as a function of temperature indicated that the effective NIOTs discharge time is temperature independent and electrons from NIOTs are emitted toward the semiconductor via-tunnelling. The NIOTs discharge time was modelled taking into account also the interface state density in a tunnelling relaxation model and it allowed to locate traps within a tunnelling distance up to 1.3nm from the SiO2/4H-SiC interface. On the other hand, sub-nm resolution STEM-EELS revealed the presence of a Non-Abrupt (NA) SiO2/4H-SiC interface. The NA interface shows the re-arrangement of the carbon atoms in a sub-stoichiometric SiOx matrix. A mixed sp2/sp3 carbon hybridization in the NA interface region suggests that the interfacial carbon atoms have lost their tetrahedral SiC coordination.

physics.app-ph↗