arXiv subjects

Mengwei Si

Publications and source records attributed to Mengwei Si.

At least 19 recordsLinked to original sources

arXiv2026

High-Performance Scaled P-Type SnOx Transistor by Atomic Layer Deposition with CFET Integration

The development of high-performance p-type oxide semiconductors is essential for realizing complementary logic for monolithic 3D integration, yet p-type oxide semiconductors still exhibit substantially inferior performance compared with their n-type counterparts. In this work, we demonstrate high-performance p-type SnOx transistors by atomic layer deposition (ALD), as back-end-of-line compatible devices for monolithic 3D integration. The SnOx transistors exhibit high field-effect mobility of 6.9 cm2/Vs, low subthreshold swing (SS) of 185 mV/dec, decent on/off ratio (ION/IOFF) of 1.8*104 and high bias stability. By scaling the channel length down to 80 nm, a high on-current of 38.7 mA/mm at VDS of -1 V is achieved. It is understood that precursor and reaction engineering to suppress Sn4+ component in SnOx film are the key for performance enhancement. Furthermore, a complementary field-effect transistor with ALD SnOx p-FET vertically stacking on ALD In2O3 n-FET is also demonstrated, achieving maximum voltage gain of 21 V/V at VDD of 4 V. These findings suggest ALD SnOx as a promising candidate for scaled high-performance BEOL p-type transistors.

cond-mat.mtrl-sci↗

arXiv2026

High-Mobility and High-Reliability Top-Gate Oxide Semiconductor Transistors by Oxygen Engineering

In this work, we investigate the role of oxygen (O) on the performance of top-gate (TG) atomic-layer-deposited (ALD) oxide semiconductor transistors. The results reveal distinct defect characteristics and positive bias temperature instability (PBTI) degradation mechanisms between oxygen-rich (O-rich) and oxygen-deficient (O-poor) devices. It is found that an O-rich device fabrication process followed by O-free annealing can effectively achieve TG indium-rich (In-rich) oxide semiconductor transistors with high mobility, high reliability and high stability in hydrogen environment because O-rich process can suppress oxygen vacancies and their interaction with hydrogen, while O-free annealing plays a critical role in minimizing the formation of O-rich defects such as oxygen dimers (O-O bonds). Consequently, TG In-rich transistors with high mobility, steep subthreshold slope, and high PBTI reliability at high temperature are demonstrated. The understanding of O-rich defects provides a new insight to overcome the mobility-stability trade-off.

cond-mat.mtrl-sci↗

arXiv2025

Dielectric Deposition Enhanced Crystallization in Atomic-Layer-Deposited Indium Oxide Transistors Achieving High Gated-Hall Mobility Exceeding 100 cm2/Vs at Room Temperature

In this work, we report high-performance atomic-layer-deposited indium oxide (In2O3) transistors with high gated-Hall mobility ({\mu}H) exceeding 100 cm2/Vs at room temperature (RT). It is found that the deposition of top hafnium oxide (HfO2) above the In2O3 channel significantly enhances its crystallization, leading to an average grain size of 97.2 nm in a 4.2-nm In2O3 channel. The ALD of In2O3 exhibits an epitaxy-like growth behavior, with its (222) planes aligning parallel to the (111) planes of both the top and bottom HfO2 dielectrics. As a result, bottom-gate In2O3 transistors with a high {\mu}H of 100.9 cm2/Vs and a decent subthreshold swing (SS) of 94 mV/dec are achieved by gated-Hall measurement at RT. Furthermore, the devices maintain excellent performance at low temperatures, achieving a {\mu}H of 162.2 cm2/Vs at 100 K. Our study reveals the critical role of dielectric deposition induced crystallization in enhancing carrier transport and offers a scalable pathway toward high-mobility devices.

cond-mat.mtrl-sci↗

arXiv2025

Are There High-Density Deep States in AtomicLayer-Deposited IGZO Thin Film?

It has been well recognized that there exist high-density deep states in IGZO thin films. Many of the device characteristics of IGZO transistors, such as negative bias illumination stability (NBIS),were understood to be related to these deep states. However, in this work, it is found that deep state density (NtD) of atomic-layer-deposited (ALD) IGZO transistors can be an ultra-low value (2.3*10^12 /cm^3) by the proposed NBIS-free light assisted I-V measurements so that the deep states do not affect the I-V characteristics even in subthreshold region. This work also reveals that NBIS is not related to the photoexcitation of electrons in deep states. Our results suggest that the existence of deep states and the impact of deep states on ALD IGZO transistors may need to be revisited.

cond-mat.mtrl-sci↗

arXiv2023

Enlargement of Memory Window of Si Channel FeFET by Inserting Al2O3 Interlayer on Ferroelectric Hf0.5Zr0.5O2

In this work, we demonstrate the enlargement of the memory window of Si channel FeFET with ferroelectric Hf0.5Zr0.5O2 by gate-side dielectric interlayer engineering. By inserting an Al2O3 dielectric interlayer between TiN gate metal and ferroelectric Hf0.5Zr0.5O2, we achieve a memory window of 3.2 V with endurance of ~105 cycles and retention over 10 years. The physical origin of memory window enlargement is clarified to be charge trapping at the Al2O3/Hf0.5Zr0.5O2 interface, which has an opposite charge polarity to the trapped charges at the Hf0.5Zr0.5O2/SiOx interface.

cond-mat.mtrl-sci↗

arXiv2022

A Nanometer-Thick Oxide Semiconductor Transistor with Ultra-High Drain Current

High drive current is a critical performance parameter in semiconductor devices for high-speed, low-power logic applications or high-efficiency, high-power, high-speed radio frequency (RF) analog applications. In this work, we demonstrate an In2O3 transistor grown by atomic layer deposition (ALD) at back-end-of-line (BEOL) compatible temperatures with a record high drain current exceeding 10 A/mm, the performance of which is 2-3 times better than all known transistors with semiconductor channels. A record high transconductance of 4 S/mm is also achieved among all transistors with a planar structure. It is found that a high carrier density and high electron velocity both contribute to this remarkably high on-state performance in ALD In2O3 transistors, which is made possible by the high-quality oxide/oxide interface, the metal-like charge-neutrality-level (CNL) alignment, and the high band velocities induced by the low density-of-state (DOS). Experimental Hall, I-V and split C-V measurements at room temperature confirm a high carrier density up to 6-7*10^13 /cm2 and a high velocity of about 10^7 cm/s. Ultra-thin oxide semiconductors, with a CNL located deep inside the conduction band, represent a promising new direction for the search of alternative channel materials for high-performance semiconductor devices.

cond-mat.mes-hall↗

arXiv2022

A Gate-All-Around Single-Channel In2O3 Nanoribbon FET with Near 20 mA/{\mu}m Drain Current

In this work, we demonstrate atomic-layer-deposited (ALD) single-channel indium oxide (In2O3) gate-all-around (GAA) nanoribbon FETs in a back-end-of-line (BEOL) compatible process. A maximum on-state current (ION) of 19.3 mA/{\mu}m (near 20 mA/{\mu}m) is achieved in an In2O3 GAA nanoribbon FET with a channel thickness (TIO) of 3.1 nm, channel length (Lch) of 40 nm, channel width (Wch) of 30 nm and dielectric HfO2 of 5 nm. The record high drain current obtained from an In2O3 FET is about one order of magnitude higher than any conventional single-channel semiconductor FETs. This extraordinary drain current and its related on-state performance demonstrate ALD In2O3 is a promising oxide semiconductor channel with great opportunities in BEOL compatible monolithic 3D integration.

physics.app-ph↗

arXiv2022

Scaled indium oxide transistors fabricated using atomic layer deposition

In order to continue to improve integrated circuit performance and functionality, scaled transistors with short channel lengths and low thickness are needed. But the further scaling of silicon-based devices and the development of alternative semiconductor channel materials that are compatible with current fabrication processes is challenging. Here we report atomic-layer-deposited indium oxide transistors with channel lengths down to 8 nm, channel thicknesses down to 0.5 nm and equivalent dielectric oxide thickness down to 0.84 nm. Due to the scaled device dimensions and low contact resistance, the devices exhibit high on-state currents of 3.1 A/mm at a drain voltage of 0.5 V and a transconductance of 1.5 S/mm at a drain voltage 1 V. Our devices are a promising alternative channel material for scaled transistors with back-end-of-line processing compatibility.

cond-mat.mtrl-sci↗

arXiv2021

Ionic control over ferroelectricity in 2D layered van der Waals capacitors

The van der Waals layered material CuInP2S6 features interesting functional behavior, including the existence of four uniaxial polarization states, polarization reversal against the electric field through Cu ion migration, a negative-capacitance regime, and reversible extraction of Cu ions. At the heart of these characteristics lies the high mobility of Cu ions, which also determines the spontaneous polarization. Therefore, Cu migration across the lattice results in unusual ferroelectric behavior. Here, we demonstrate how the interplay of polar and ionic properties provides a path to ionically controlled ferroelectric behavior, achieved by applying selected DC voltage pulses and subsequently probing ferroelectric switching during fast triangular voltage sweeps. Using current measurements and theoretical calculations, we observe that increasing DC pulse duration results in higher ionic currents, the build-up of an internal electric field that shifts polarization loops, and an increase in total switchable polarization by ~50% due to the existence of a high polarization phase which is stabilized by the internal electric field. Apart from tuning ferroelectric behavior by selected square pulses, hysteretic polarization switching can even be entirely deactivated and reactivated, resulting in three-state systems where polarization switching is either inhibited or can be performed in two different directions.

cond-mat.mtrl-sci↗

arXiv2021

Bilayer Quantum Hall States in an n-type Wide Tellurium Quantum Well

Tellurium (Te) is a narrow bandgap semiconductor with a unique chiral crystal structure. The topological nature of electrons in the Te conduction band can be studied by realizing n-type doping using atomic layer deposition (ALD) technique on two-dimensional (2D) Te film. In this work, we fabricated and measured the double-gated n-type Te Hall-bar devices, which can operate as two separate or coupled electron layers controlled by the top gate and back gate. Profound Shubnikov-de Haas (SdH) oscillations are observed in both top and bottom electron layers. Landau level hybridization between two layers, compound and charge-transferable bilayer quantum Hall states at filling factor 4, 6, and 8 are analyzed. Our work opens the door for the study of Weyl physics in coupled bilayer systems of 2D materials.

cond-mat.mes-hall↗

arXiv2021

The Critical Role of Charge Balance on the Memory Characteristics of Ferroelectric Field-Effect Transistors

Ferroelectric field-effect transistors (Fe-FETs) with ferroelectric hafnium oxide (FE HfO2) as gate insulator are being extensively explored as a promising device candidate for three-dimensional (3D) NAND memory application. FE HfO2 exhibits long retention over 10 years, high endurance over 1012 cycles, high speed with sub-ns polarization switching, and high remnant polarization of 10-30 {\mu}C/cm2. However, the performance of Fe-FETs is known to be much worse than FE HfO2 capacitors, which is not completely understood. In this work, we developed a comprehensive Fe-FET model based on a charge balance framework. The role of charge balance and the impact of leakage-assist-switching mechanism on the memory characteristics of Fe-FETs with M/FE/DE/S (Metal/Ferroelectric/Dielectric/Semiconductor) gate stack is studied. It is found that the FE/DE interface and DE layer instead of FE layer is critical to determine the memory characteristics of Fe-FETs, and experimental Fe-FETs can be well explained by this model, where the discrepancy between FE capacitors and Fe-FETs are successfully understood.

cond-mat.mes-hall↗

arXiv2021

Multi-domain Polarization Switching in Hf0.5Zr0.5O2-Dielectric Stack: The Role of Dielectric Thickness

We investigate the polarization switching mechanism in ferroelectric-dielectric (FE-DE) stacks and its dependence on the dielectric thickness (TDE). We fabricate HZO-Al2O3 (FE-DE) stack and experimentally demonstrate a decrease in remnant polarization and an increase in coercive voltage of the FE-DE stack with an increase in TDE. Using phase-field simulations, we show that an increase in TDE results in a larger number of reverse domains in the FE layer to suppress the depolarization field, which leads to a decrease in remanent polarization and an increase in coercive voltage. Further, the applied voltage-driven polarization switching suggests domain-nucleation dominant characteristics for low TDE, and domain-wall motion-induced behavior for higher TDE. In addition, we show that the hysteretic charge-voltage characteristics of the FE layer in the FE-DE stack exhibit a negative slope region due to the multi-domain polarization switching in the FE layer. Based on our analysis, the trends in charge-voltage characteristics of the FE-DE stack with respect to different TDE (which are out of the scope of single-domain models) can be described well with multi-domain polarization switching mechanisms.

physics.app-ph↗

arXiv2021

First Demonstration of Robust Tri-Gate \b{eta}-Ga2O3 Nano-membrane Field-Effect Transistors Operated Up to 400 {\deg}C

Nano-membrane tri-gate beta-gallium oxide (\b{eta}-Ga2O3) field-effect transistors (FETs) on SiO2/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized features can be defined with a 50 nm fin structure. For high-quality interface between \b{eta}-Ga2O3 and gate dielectric, atomic layer-deposited 15-nm-thick aluminum oxide (Al2O3) was utilized with Tri-methyl-aluminum (TMA) self-cleaning surface treatment. The fabricated devices demonstrate extremely low subthreshold slope (SS) of 61 mV/dec, high drain current (IDS) ON/OFF ratio of 1.5 X 109, and negligible transfer characteristic hysteresis. We also experimentally demonstrated robustness of these devices with current-voltage (I-V) characteristics measured at temperatures up to 400 {\deg}C.

physics.app-ph↗

arXiv2020

Why In2O3 Can Make 0.7 nm Atomic Layer Thin Transistors?

In this work, we demonstrate enhancement-mode field-effect transistors by atomic-layer-deposited (ALD) amorphous In2O3 channel with thickness down to 0.7 nm. Thickness is found to be critical on the materials and electron transport of In2O3. Controllable thickness of In2O3 at atomic scale enables the design of sufficient 2D carrier density in the In2O3 channel integrated with the conventional dielectric. The threshold voltage and channel carrier density are found to be considerably tuned by channel thickness. Such phenomenon is understood by the trap neutral level (TNL) model where the Fermi-level tends to align deeply inside the conduction band of In2O3 and can be modulated to the bandgap in atomic layer thin In2O3 due to quantum confinement effect, which is confirmed by density function theory (DFT) calculation. The demonstration of enhancement-mode amorphous In2O3 transistors suggests In2O3 is a competitive channel material for back-end-of-line (BEOL) compatible transistors and monolithic 3D integration applications.

cond-mat.mtrl-sci↗

arXiv2020

Scaled Atomic-Layer-Deposited Indium Oxide Nanometer Transistors with Maximum Drain Current Exceeding 2 A/mm at Drain Voltage of 0.7 V

In this work, we demonstrate scaled back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors by atomic layer deposition (ALD) with channel thickness (Tch) of 1.0-1.5 nm, channel length (Lch) down to 40 nm, and equivalent oxide thickness (EOT) of 2.1 nm, with record high drain current of 2.0 A/mm at VDS of 0.7 V among all oxide semiconductors. Enhancement-mode In2O3 transistors with ID over 1.0 A/mm at VDS of 1 V are also achieved by controlling the channel thickness down to 1.0 nm at atomic layer scale. Such high current density in a relatively low mobility amorphous oxide semiconductor is understood by the formation of high density 2D channel beyond 4E13 /cm2 at HfO2/In2O3 oxide/oxide interface.

cond-mat.mtrl-sci↗

arXiv2020

Indium-Tin-Oxide Transistors with One Nanometer Thick Channel and Ferroelectric Gating

In this work, we demonstrate high performance indium-tin-oxide (ITO) transistors with the channel thickness down to 1 nm and ferroelectric Hf0.5Zr0.5O2 as gate dielectric. On-current of 0.243 A/mm is achieved on sub-micron gate-length ITO transistors with a channel thickness of 1 nm, while it increases to as high as 1.06 A/mm when the channel thickness increases to 2 nm. A raised source/drain structure with a thickness of 10 nm is employed, contributing to a low contact resistance of 0.15 Ωmm and a low contact resistivity of 1.1{\times}10-7 Ωcm2. The ITO transistor with a recessed channel and ferroelectric gating demonstrates several advantages over 2D semiconductor transistors and other thin film transistors, including large-area wafer-size nanometer thin film formation, low contact resistance and contact resistivity, atomic thin channel being immunity to short channel effects, large gate modulation of high carrier density by ferroelectric gating, high-quality gate dielectric and passivation formation, and a large bandgap for the low-power back-end-of-line (BEOL) CMOS application.

physics.app-ph↗

arXiv2020

$α$-In$_2$Se$_3$ based Ferroelectric-Semiconductor Metal Junction for Non-Volatile Memories

In this work, we theoretically and experimentally investigate the working principle and non-volatile memory (NVM) functionality of 2D $α$-In$_2$Se$_3$ based ferroelectric-semiconductor-metal-junction (FeSMJ). First, we analyze the semiconducting and ferroelectric properties of $α$-In$_2$Se$_3$ van-der-Waals (vdW) stack via experimental characterization and first-principle simulations. Then, we develop a FeSMJ device simulation framework by self-consistently solving Landau-Ginzburg-Devonshire (LGD) equation, Poisson's equation, and charge-transport equations. Based on the extracted FeS parameters, our simulation results show good agreement with the experimental characteristics of our fabricated $α$-In$_2$Se$_3$ based FeSMJ. Our analysis suggests that the vdW gap between the metal and FeS plays a key role to provide FeS polarization-dependent modulation of Schottky barrier heights. Further, we show that the thickness scaling of FeS leads to a reduction in read/write voltage and an increase in distinguishability. Array-level analysis of FeSMJ NVM suggests a 5.47x increase in sense margin, 18.18x reduction in area and lower read-write power with respect to Fe insulator tunnel junction (FTJ).

physics.app-ph↗

arXiv2020

Quantum Hall Effect of Weyl Fermions in Semiconducting n-type Tellurene

Dirac and Weyl nodal materials can host low-energy relativistic quasiparticles. Under strong magnetic fields, the topological properties of Dirac/Weyl materials can directly manifest through quantum Hall states. However, most Dirac/Weyl nodes generically exist in semimetals without exploitable bandgaps due to their accidental band-crossing origin. Here we report the first experimental observation of Weyl fermions in a semiconductor. Tellurene, the 2D form of tellurium, possesses chiral crystal structure which induces unconventional Weyl nodes with a hedgehog-like radial spin texture near the conduction band edge. We synthesize high-quality n-type tellurene by a hydrothermal method with subsequent dielectric doping and detect a topologically non-trivial pi Berry phase in quantum Hall sequences. Our work expands the spectrum of Weyl matter into semiconductors and offers a new platform to design novel quantum devices by marrying the advantages of topological materials to versatile semiconductors.

cond-mat.mes-hall↗