arXiv subjects

Paolo Durante

Publications and source records attributed to Paolo Durante.

4 recordsLinked to original sources

arXiv2026

PCIe400 generic readout board qualification test

The PCIe400 is a generic readout board designed for high-throughput data acquisition in future high-energy physics experiments. It interfaces up to 48 bidirectional links supporting custom protocols from 1 to 26 Gbps to modern back-end systems providing up to 400 Gbps bandwidth.The board is developed as a technological demonstrator for the LHCb Upgrade II, which foresees an aggregated throughput of approximately 200 Tbps. In addition to increased bandwidth, the PCIe400 targets deterministic clock distribution to front-end electronics. At a maximum instantaneous luminosity of $1.5~\times~10^{34}~cm^{-2}s^{-1}$, up to 40 proton-proton interactions per bunch crossing are expected in LHCb Upgrade II. The adoption of 4D tracking detectors with time resolutions down to 20 ps motivates clock distribution with phase determinism below 10 ps peak-to-peak across large-scale systems exceeding 2000 nodes. This paper presents the qualification of the PCIe400 prototype board, focusing on high-bandwidth interfaces, including next-generation QSFP112 links, and phase-deterministic clock distribution.

physics.ins-det↗

arXiv2025

A Low-Cost, Low-Power Media Converter Solution for Next-Generation Detector Readout Systems

High Energy Physics (HEP) data acquisition systems are often built from high-end FPGAs. As such systems scale in the HL-LHC era, severe under-utilization of FPGA transceivers can occur because front-end links prioritize radiation hardness and power consumption over raw data bandwidth. This work evaluates recently introduced low-power, low-cost FPGA devices as an alternative building block for future readout architectures. This study presents the implementation of a readout back-End on FPGA where the front-end protocol is based on the Low-Power GigaBit Transceiver (lpGBT) and the readout protocol is based on 10 Gigabit Ethernet, using the LHCb Run 4 RICH detector as a practical case study.

physics.ins-det↗

arXiv2018

The readout supervisor firmware for controlling the upgraded LHCb detector and readout system

In 2019, the LHCb experiment at CERN will undergo a major upgrade where its detector electronics and the entire readout system will be replaced. The goal is to read-out all events at the full LHC frequency of 40 MHz, reaching a total data rate of ~40 Tb/s. In this context, a new timing, trigger and readout control system has been developed: its main tasks are to distribute centrally the clock, the timing information and to synchronize all elements in the readout system: from the very last Front-End ASIC to the building of events to be stored. The heart of the timing and readout control system is a VHDL firmware core that is now finalized and currently in use in test-benches and test-beams by the upgraded sub-detectors, for their initial commissioning phase. Such firmware core is able to generate all necessary processes to keep the synchronization of all readout elements with the LHC bunch crossing as well as it is able to generate asynchronous commands for calibration or test purposes. It is also able to accommodate for specific recipes to handle varying running conditions, by using a generic and fully configurable approach. In this paper, the philosophy and the implementation behind such firmware are described in details, posing particular emphasis to the real-time logical processes that were developed in order to satisfy the requirements of synchronization and readout control of the upgraded LHCb detector.

physics.ins-det↗

arXiv2018

FLIT-level InfiniBand network simulations of the DAQ system of the LHCb experiment for Run-3

The LHCb (Large Hadron Collider beauty) experiment is designed to study differences between particles and anti-particles as well as very rare decays in the charm and beauty sector at the LHC (Large Hadron Collider). The detector will be upgraded in 2019 and a new trigger-less readout system will be implemented in order to significantly increase its efficiency and take advantage of the increased machine luminosity. In the upgraded system, both event building and event filtering will be performed in software for all the data produced in every bunch-crossing of the LHC. In order to transport the full data rate of 32 Tb/s we will use custom FPGA readout boards (PCIe40) and state of the art off-the-shelf network technologies. The full event building system will require around 500 nodes interconnected together. From a networking point of view, event building traffic has an all-to-all pattern, therefore it tends to create high network congestion. In order to maximize the link utilization different techniques can be adopted in various areas like traffic shaping, network topology and routing optimization. The size of the system makes it very difficult to test at production scale, before the actual procurement. We resort therefore to network simulations as a powerful tool for finding the optimal configuration. We will present an accurate low level description of an InfiniBand based network with event building like traffic. We will show comparison between simulated and real systems and how changes in the input parameters affect performances.

cs.NI↗