arXiv subjects

S. Hou

Publications and source records attributed to S. Hou.

At least 19 recordsLinked to original sources

arXiv2026

Real-Time Wiener Deconvolution for feature reconstruction in JUNO

In particle physics, experiments generate substantial amounts of data that can be difficult to process without preliminary scaling. To avoid losing potentially crucial data, experimental collaborations are studying novel techniques for real-time data processing to extract features for further physics analysis. A common approach, especially in neutrino physics, is to use FPGAs for data acquisition and pre-processing. This paper presents an advanced Real-Time Wiener deconvolution algorithm designed to leverage the processing capabilities of the FPGA integrated into the readout boards of the Jiangmen Underground Neutrino Observatory (JUNO). The goal is to enable real-time reconstruction of the signal generated by photomultiplier tubes (PMTs) when neutrino interactions are detected. By exploiting online reconstruction of the signal generated by PMTs, we expect to improve the detection of low-energy depositions, such as those produced by transient astrophysical phenomena. These depositions are usually not saved because of the significant background that affects the low end of the energy spectrum, which would result in a large trigger rate, hence a large amount of data required for storage. This paper presents the features of the algorithm, including its ability to manage high-throughput data streams with minimal latency, adaptability, and resilience in discerning the characteristics of input data. Performance is evaluated on a JUNO electronic board. This study further demonstrates the potential of FPGA-based solutions for neutrino physics.

physics.ins-det↗

arXiv2025

Beam-test evaluation of pre-production Low Gain Avalanche Detectors for the ATLAS High Granularity Timing Detector

The High Granularity Timing Detector (HGTD) will be installed in the ATLAS experiment as part of the Phase-II upgrade for the High Luminosity-Large Hadron Collider (HL-LHC). It will mitigate pile-up effects in the forward region, and measure per bunch luminosity. The design of HGTD is based on Low Gain Avalanche Detector (LGAD) sensors. This paper presents the results of beam-test campaigns conducted at CERN and DESY in 2023 and 2024 on single LGADs from HGTD pre-production test structures, before and after neutron irradiation up to fluences of $2.5 \times 10^{15}~\mathrm{n_{eq}/cm^2}$. The tested LGADs can meet HGTD requirements in terms of charge collection, time resolution, and hit efficiency, even under HL-LHC end-of-life conditions, supporting their deployment in the final detector.

physics.ins-det↗

arXiv2025

Thermal Cycling Reliability of Hybrid Pixel Sensor Modules for The ATLAS High Granularity Timing Detector

The reliability of bump connection structures has become a critical aspect of future silicon detectors for particle physics. The High Granularity Timing Detector (HGTD) for the ATLAS experiment at the High-Luminosity Large Hadron Collider will require 8032 hybrid pixel sensor modules, composed of two Low Gain Avalanche Diode sensors bump-bonded to two readout ASICs and glued to a passive PCB. The detector will operate at low temperature (-30 degrees Celsius) to mitigate the impact of irradiation. The thermomechanical reliability of flip-chip bump connections in HGTD modules is a critical concern, particularly due to their characteristically lower bump density (pixel pitch dimensions of 1.3 mm by 1.3 mm). This paper elaborates on the challenges arising from this design characteristic. Finite element analysis and experimental testing were employed to investigate failure modes in the flip-chip bump structures under thermal cycling from -45 degrees Celsius to 40 degrees Celsius and to guide the module redesign. The optimized design demonstrates significantly enhanced robustness and is projected to fulfill the full lifetime requirements of the HGTD.

physics.ins-det↗

arXiv2024

Characteristics of the MTx optical transmitter in Total Ionizing Dose

The dual-channel multi-mode 850 nm optical Miniature Transmitter (MTx) is developed for data transmission of the ATLAS LAr calorimeter readout at LHC. The MTx's are exposed to the radiation field of proton-proton collisions, therefore, the tolerance in Total Ionizing Dose (TID) is required. The TID effects in the MTx are investigated with X-rays and Co-60 gamma-rays for the active components of VCSEL diodes and the customized Link-on-Chip laser driver (LOCld) developed in 0.25 um Silicon-on-Sapphire CMOS technology. The irradiation tests were conducted at various dose rates. The responses to TID are observed with degradation of laser currents at initial dose of 10 to 100 Gy(SiO2), and partial recovery with additional TID to a stable output about 90 % of the original. The optical eye diagrams of irradiated samples show slightly increased jittering, and are suitable for the ATLAS requirement of 5 Gbps applications.

physics.ins-det↗

arXiv2023

The New Small Wheel electronics

The increase in luminosity, and consequent higher backgrounds, of the LHC upgrades require improved rejection of fake tracks in the forward region of the ATLAS Muon Spectrometer. The New Small Wheel upgrade of the Muon Spectrometer aims to reduce the large background of fake triggers from track segments that are not originated from the interaction point. The New Small Wheel employs two detector technologies, the resistive strip Micromegas detectors and the "small" Thin Gap Chambers, with a total of 2.45 Million electrodes to be sensed. The two technologies require the design of a complex electronics system given that it consists of two different detector technologies and is required to provide both precision readout and a fast trigger. It will operate in a high background radiation region up to about 20 kHz/cm$^{2}$ at the expected HL-LHC luminosity of $\mathcal{L}$=7.5$\times10^{34}$cm$^{-2}$s$^{-1}$. The architecture of the system is strongly defined by the GBTx data aggregation ASIC, the newly-introduced FELIX data router and the software based data handler of the ATLAS detector. The electronics complex of this new detector was designed and developed in the last ten years and consists of multiple radiation tolerant Application Specific Integrated Circuits, multiple front-end boards, dense boards with FPGA's and purpose-built Trigger Processor boards within the ATCA standard. The New Small Wheel has been installed in 2021 and is undergoing integration within ATLAS for LHC Run 3. It should operate through the end of Run 4 (December 2032). In this manuscript, the overall design of the New Small Wheel electronics is presented.

hep-ex↗

arXiv2023

GBT20, a 20.48 Gbps PAM4 Optical Transmitter Module for Particle Physics Experiments

We present a pluggable radiation-tolerant 4-level Pulse-Amplitude-Modulation (PAM4) optical transmitter module called GBT20 (Giga-Bit Transmitter at 20 Gbps) for particle-physics experiments. GBT20 has an OSFP or firefly connector to input 16-bit data each at 1.28 Gbps. The GBT20 drives a VCSEL die with an LC lens or a VCSEL TOSA and interfaces an optical fiber with a standard LC connector. The minimum module, including the host connector, occupies 41 mm x 13 mm x 6 mm. At 20.48 Gbps, the minimum Transmitter Dispersion Eye Closure Quaternary (TDECQ) is around 0.7 dB. The power consumption is around 164 mW in the low-power mode. The SEE cross-section is below 7.5x10^(-14) cm^2. No significant performance degrades after a TID of 5.4 kGy.

physics.ins-det↗

arXiv2023

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8*10^(-16), significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.

physics.ins-det↗

arXiv2022

A 40 Gbps Optical Transceiver for Particle Physics Experiments

We present the design and the test results of a quad-channel optical transceiver module (QTRx) possibly for future particle physics experiments. The transmitters of QTRx, each at 10 Gbps, are based on a Quad-channel VCSEL Diode array Driver (QLDD) and 1 x 4 VCSEL array. The receivers of QTRx, with data rates of 2.56 Gbps or 10 Gbps per channel, are based on a Quad-channel Trans-Impedance and limiting Amplifier (QTIA) and 1 x 4 photodiode array of GaAs or InGaAs. QTRx is 20 mm x 10 mm x 5 mm and couples to an MT fiber connector. Test results indicate that QTRx achieves the design goals with a power consumption of 124 mW per transmitter channel at 10 Gbps and 120 mW at 2.56 Gbps for the receiver channel with an on-chip charge pump. The sensitivities of QTIA are -17 dBm at 2.56 Gbps and -8 dBm at 10 Gbps, respectively. Further improvements with a gold-finger interface and a more compact optical lens are being designed.

physics.ins-det↗

arXiv2022

A prototype optical link board with redundancy design for the ATLAS liquid argon calorimeter Phase-2 upgrade

A prototype optical-link board has been developed for the ATLAS Liquid Argon Calorimeter Phase-2 upgrade. The board consists of 24 lpGBT chips and 8 VTRx+ modules and demonstrates the full optical link design of the future front-end board. The board has 22 simplex optical links to transmit detector data, which are emulated in FPGAs and injected through 6 FMC connectors, to the off-detector electronics. The board implements 2 duplex optical links for clocks, control, and monitoring with redundant design to improve the system reliability. Data transmission and all redundant designs have been verified. A fiber routing scheme, in which 2 or 3 VTRx+ modules are re-connected to the front panel with an MPO connector, has been prototyped.

physics.ins-det↗

arXiv2022

A 20 Gbps PAM4 Data Transmitter ASIC for Particle Physics Experiments

We present the design and test results of a novel data transmitter ASIC operating up to 20.48 Gbps with 4-level Pulse-Amplitude-Modulation (PAM4) for particle physics experiments. This ASIC, named GBS20, is fabricated in a 65 nm CMOS technology. Two serializers share a 5.12 GHz Phase Locked Loop (PLL) clock. The outputs from the serializers are combined into a PAM4 signal that directly drives a Vertical-Cavity-Surface-Emitting-Laser (VCSEL). The input data channels, each at 1.28 Gbps, are scrambled with an internal 27-1 Pseudo-Random Binary Sequence (PRBS), which also serves as a frame aligner. GBS20 is tested to work at 10.24 and 20.48 Gbps with a VCSEL-based Transmitter-Optical-Subassembly (TOSA). The power consumption of GBS20 is below 238 mW and reduced to 164 mW in the low-power mode.

physics.ins-det↗

arXiv2021

QTIA, a 2.5 or 10 Gbps 4-Channel Array Optical Receiver ASIC in a 65 nm CMOS Technology

The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed the lab tests with GaAs photodiodes.

physics.ins-det↗

arXiv2021

Quality control tests of the front-end optical link components for the ATLAS Liquid Argon Calorimeter Phase-1 upgrade

We present the procedures and results of the quality control tests for the front-end optical link components in the ATLAS Liquid Argon Calorimeter Phase-1 upgrade. The components include a Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC LOCld, custom optical transmitter/transceiver modules MTx/MTRx, and a transmitter ASIC LOCx2. LOCld, MTx, and LOCx2 each contain two channels with the same structure, while MTRx has a transmitter channel and a receiver channel. Each channel is tested at 5.12 Gbps. A total of 5341 LOCld chips, 3275 MTx modules, 797 MTRx modules, and 3198 LOCx2 chips are qualified. The yields are 73.9%, 98.0%, 98.4%, and 61.9% for LOCld, LOCx2, MTx, and MTRx, respectively.

physics.ins-det↗

arXiv2021

Characterization and quality control test of a gigabit cable receiver ASIC (GBCR2) for the ATLAS Inner Tracker Detector upgrade

We present the characterization and quality control test of a gigabit cable receiver ASIC prototype, GBCR2, for the ATLAS Inner Tracker pixel detector upgrade. GBCR2 equalizes and retimes the uplink electrical signals from RD53B through a 6 m Twinax AWG34 cable to lpGBT. GBCR2 also pre-emphasizes downlink command signals through the same electrical connection from lpGBT to RD53B. GBCR2 has seven uplink channels each at 1.28 Gbps and two downlink channels each at 160 Mbps. The prototype is fabricated in a 65 nm CMOS process. The characterization of GBCR2 has been demonstrated that the total jitter of the output signal is 129.1 ps (peak-peak) in the non-retiming mode or 79.3 ps (peak-peak) in the retiming mode for the uplink channel and meets the requirements of lpGBT. The total power consumption of all uplink channels is 87.0 mW in the non-retiming mode and 101.4 mW in the retiming mode, below the specification of 174 mW. The two downlink channels consume less than 53 mW. A quality control test procedure is proposed and 169 prototype chips are tested. The yield is about 97.0%.

physics.ins-det↗

arXiv2021

Graphene-based Distributed 3D Sensing Electrodes for Mapping Spatiotemporal Auricular Physiological Signals

Underneath the ear skin there are richly branching vascular and neural networks that ultimately connecting to our heart and brain. Hence, the three-dimensional (3D) mapping of auricular electrophysiological signals could provide a new perspective for biomedical studies such as diagnosis of cardiovascular diseases and neurological disorders. However, it is still extremely challenging for current sensing techniques to cover the entire ultra-curved auricle. Here, we report a graphene-based ear-conformable sensing device with embedded and distributed 3D electrodes which enable full-auricle physiological monitoring. The sensing device, which incorporates programable 3D electrode thread array and personalized auricular mold, has 3D-conformable sensing interfaces with curved auricular skin, and was developed using one-step multi-material 3D-printing process. As a proof-of-concept, spatiotemporal auricular electrical skin resistance (AESR) mapping was demonstrated. For the first time, 3D AESR contours were generated and human subject-specific AESR distributions among a population were observed. From the data of 17 volunteers, the auricular region-specific AESR changes after cycling exercise were observed in 98% of the tests and were validated via machine learning techniques. Correlations of AESR with heart rate and blood pressure were also studied using statistical analysis. This 3D electronic platform and AESR-based new biometrical findings show promising biomedical applications.

eess.SP↗

arXiv2020

A novel quad-channel 10 Gbps CMOS VCSEL array driver with integrated charge pumps

We present a novel design and the test results of a 4-channel driver for an array of Vertical-Cavity Surface-Emitting Lasers (VCSELs). This ASIC, named cpVLAD and fabricated in a 65 nm CMOS technology, has on-chip charge pumps and is for data rates up to 10 Gbps per channel. The charge pumps are implemented to address the issue of voltage margin of the VCSEL driving stage in the applications under low temperature and harsh radiation environment. Test results indicate that cpVLAD is capable of driving VCSELs with forward voltages of up to 2.8 V using 1.2 V and 2.5 V power supplies with a power consumption of 94 mW/channel.

physics.ins-det↗

arXiv2020

Optical transceivers for event triggers in the ATLAS phase-I upgrade

The ATLAS phase-I upgrade aims to enhance event trigger performance in the Liquid Argon (LAr) calorimeter and the forward muon spectrometer. The trigger signals are transmitted by optical transceivers at 5.12 Gbps per channel in a radiation field. We report the design, quality control in production and ageing test of the transceivers fabricated with the LOCld laser driver and multi-mode 850 nm vertical-cavity surface-emitting laser (VCSEL). The modules are packaged in miniature formats of dual-channel transmitter (MTx) and transceiver (MTRx) for the LAr. The transmitters are also packaged in small form-factor pluggable (SFP) for the muon spectrometer. In production, the LOCld chips and VCSELs in TOSA package were examined before assembly. All of the modules were tested and selected during production for quality control based on the eye-diagram parameters measured at 5.12 Gbps. The yield is 98 % for both the MTx and MTRx on a total 4.7k modules. The uniformity of transmitter channels of a MTx was assured by choosing the TOSA components with approximately equal light powers. The ageing effect is monitored in burn-in of a small batch of transmitter modules with bit-error test and eye-diagrams measured periodically. The observables are stable with the light power degradation within 5 % over a period of more than 6k hours.

physics.ins-det↗

arXiv2020

A 4-Channel 10-Gbps/ch CMOS VCSEL Array Driver with on-chip Charge-pumps

We present the design and test results of a 4-channel 10-Gbps/ch Vertical-Cavity Surface-Emitting Laser array driver, the cpVLAD. With on-chip charge-pumps to extend the biasing headroom for the VCSELs needed for low temperature operation and mitigation of the radiation effects. The cpVLAD was fabricated in a 65-nm CMOS technology. The test results show that the cpVLAD is capable of driving VCSELs with forward bias voltages as high as 2.8 V from a 2.5 V power supply. The power consumption of the cpVLAD is 94 mW/ch.

physics.ins-det↗

arXiv2020

A TOSA/ROSA-Based Optical Transmitter (MTx+)/Transceiver (MTRx+) for High-Energy Physics Experiments

We present a dual-channel optical transmitter (MTx+)/transceiver (MTRx+) for the front-end readout electronics of high-energy physics experiments. MTx+ utilizes two Transmitter Optical Sub-Assemblies (TOSAs) and MTRx+ utilizes a TOSA and a Receiver Optical Sub-Assemblies (ROSA). Both MTx+ and MTRx+ receive multimode fibers with standard Lucent Connectors (LCs) as the optical interface and can be panel or board mounted to a motherboard with a standard Enhanced Small Form-factor Pluggable (SFP+) connector as the electrical interface. MTx+ and MTRx+ employ a dual-channel Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC called LOCld65, which brings the transmitting data rate up to 14 Gbps per channel. MTx+ and MTRx+ have been tested to survive 4.9 kGy(SiO2).

physics.ins-det↗