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Samuel Stein

Publications and source records attributed to Samuel Stein.

At least 19 recordsLinked to original sources

Encoding Choices and Fault-Tolerant Resource Estimates for Digital Quantum Hamiltonian Descent

Quantum Hamiltonian descent (QHD) formulates continuous optimization as time-dependent quantum dynamics, where a kinetic term drives exploration and a potential term encodes the objective function. Digital implementations of QHD require encoding the search space into qubits, and this choice can shift the dominant cost among logical qubits, circuit depth, non-Clifford rotations, and potential synthesis. In this work, we present an encoding-aware resource analysis comparing one-hot and binary amplitude encodings for QHD. We derive gate-count scalings, construct and validate circuits against classical \Sch-equation solvers, and estimate Clifford+$R_z$ and fault-tolerant Clifford+$T$ resources on benchmark optimization problems. Binary encoding reduces the data register from $O(dN)$ to $O(d\log N)$ qubits and gives comparable asymptotic scaling for both kinetic and potential evolutions. Across all benchmark problems studied, binary encoding also uses fewer $R_z$ rotations than one-hot encoding, making it the preferred option for fault-tolerant implementations where arbitrary rotations dominate the cost. Kinetic approximations based on low-momentum spectra and approximate QFTs can further reduce the binary kinetic cost to polylogarithmic scaling. However, for targets such as Ackley, potential synthesis can dominate the total cost and reduce the benefit of kinetic approximations. These results suggest that exploiting the analytic structure of the target function to compile the potential evolution in QHD more efficiently is needed for further resource reductions.

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Benchmarking and Resource Analysis for Augmented-Lagrangian Quantum Hamiltonian Descent

Quantum Hamiltonian Descent (QHD) is a continuous optimization algorithm based on simulating a time-dependent quantum Hamiltonian whose potential energy encodes the objective function and whose kinetic energy promotes exploration through quantum interference and tunneling. While QHD is formulated for unconstrained optimization, many real-world optimization problems are constrained and highly nonconvex. In this paper, we benchmark AL-QHD, a hybrid framework that embeds QHD within the Augmented Lagrangian Method (ALM), thereby solving a sequence of unconstrained subproblems while using ALM to enforce constraints. We evaluate AL-QHD on standard nonconvex test functions and use iterative refinement to improve solution accuracy at fixed per-run qubit cost. We also perform a gate-based resource analysis on ACOPF-derived power system subproblems constructed from power-network data to estimate the quantum-computer scale required for practical applications. Resource estimates on Texas7k-derived ACOPF instances show steep hard-gate scaling, reaching $\sim 4.46 \times 10^7$ entangling gates in a NISQ-oriented model and $\sim 9.42 \times 10^8$ T gates in a fault-tolerant model at $\sim 5.3 \times 10^2$ active variables. These results suggest that AL-QHD is a useful framework for studying constrained nonconvex optimization with QHD, but that practical ACOPF-scale applications would likely require large-scale fault-tolerant quantum hardware.

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FTPrimitiveBench: A Benchmark Suite For Logical Computation Under Hardware-Motivated and Biased Noise Models

Fault-tolerant quantum computing requires understanding how error-correcting codes perform on diverse physical hardware. This is typically assessed via noisy stabilizer simulation of logical circuits at HPC scale, combined with a noise model that yields a logical error rate for the relevant code distances and depths. The uniform depolarizing model is the standard baseline, but its homogeneous assumptions fail to capture the heterogeneity, asymmetries, and correlations of real devices, where Pauli, measurement, and spatio-temporal errors are not weakly coupled. Yet these same structured features create opportunities for joint code-hardware co-design, motivating noise models that more faithfully reflect target hardware while remaining tractable to simulate. We introduce FTPrimitiveBench, a systematic benchmarking approach for studying how logical primitives interact with hardware-motivated noise. It supports both custom specifications and representative structured noise families: Pauli bias, measurement bias, and spatial or spatio-temporal non-uniformity -- together with generators for core surface-code Clifford primitives: logical memory, lattice surgery, transversal logical Hadamard, and the logical phase gate via lattice surgery. We find that structured noise affects these primitives in qualitatively distinct ways, with outcomes shaped by the interplay between noise model, primitive, and decoder choice. These results extend memory benchmarks to active logical computation, where the interaction between noise structure and primitive implementation matters. By standardizing the link between noise-model specification and primitive construction, FTPrimitiveBench enables reproducible comparative studies of QEC protocols and decoders, supporting hardware-aware co-design of fault-tolerant architectures. Code: https://github.com/ShuwenKan/FTPrimitiveBench.

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Benchmarking quantum trial wavefunctions for phaseless auxiliary-field quantum Monte Carlo

The phaseless auxiliary-field quantum Monte Carlo (ph-AFQMC) method is a stochastic imaginary-time projection technique for computing ground-state properties of strongly correlated quantum systems, with accuracy that depends critically on the choice of trial wavefunction. Here, we investigate ph-AFQMC with trial states prepared using parameterized quantum circuits. In this work, we present a comprehensive benchmarking study of quantum trial wavefunctions spanning unitary coupled-cluster, Hamiltonian-informed, Jastrow-inspired, and adaptively constructed ansatze. The benchmarking evaluates accuracy, expressibility, and scalability of these ansatze within the QC-AFQMC framework. We test these ansatze on linear hydrogen chains under bond stretching and find that several ansatz families produce chemically accurate ph-AFQMC energies across the dissociation curve. We have performed simulations using the CUDA-Q quantum development platform on the GPU partition of the Perlmutter supercomputer. When comparing ansatze at similar numbers of variational parameters, we find that different ansatz families yield comparable ph-AFQMC results despite exhibiting substantially different variational energies, optimization costs, and circuit depths. Our results indicate that the variational energy of an ansatz is not always a reliable indicator of its quality for ph-AFQMC and reveal instances of over-parameterization. In the strongly correlated regime, trial wavefunctions obtained from adaptive ansatze, exemplified here by ADAPT-VQE with the UCCSD operator pool, can outperform their fixed-ansatz counterparts (UCCSD) in terms of projected energies while using substantially more compact circuits, providing a flexible route to optimize quantum resources within the ph-AFQMC framework.

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QASMTrans: An End-to-End QASM Compilation Framework with Pulse Generation for Near-Term Quantum Devices

QASMTrans is a lightweight, high-performance, C++-based quantum compiler that bridges abstract quantum algorithms to device-level control and is designed for just-in-time (JIT) deployment on QPU testbeds with tightly integrated FPGAs or CPUs. We focus on achieving fast transpilation times on circuits of interest, we find more than 100x faster compilation than Qiskit in some circuits with similar circuit quality, enabling transpilation of large, high-depth circuits in seconds. Unlike existing tools, QASMTrans offers end-to-end device-pulse compilation and direct quantum control integration with QICK, closing the gap between logical circuits and hardware control enabling closed-loop optimization. QASMTrans supports latency-aware Application-tailored Gate Sets (AGS) at the pulse level, identifying high-impact gate sequences on the circuit critical path and synthesizing optimized pulse schedules using pre-defined robust circuit ansatz. Validated through integrated QuTiP pulse-level simulation, this is found to significantly reduce execution latency and can improve final-state fidelity by up to 12% in some tested circuits. QASMTrans further implements device-aware, noise-adaptive transpilation that uses device calibration data for circuit placement on high-quality qubits and can focus on the circuit critical path to reduce transpilation-pass time while maintaining comparable fidelity. Additionally, it introduces circuit space sharing via calibration-aware device partitioning, enabling concurrent execution of multiple circuits or shots on a single QPU. Moreover, QASMTrans is entirely self-contained and has no external library dependencies, making it easy for practical deployment. By combining fast compilation, pulse-level control, and noise-aware optimization, QASMTrans enables real-time adaptive algorithms such as ADAPT-VQE and ADAPT-QAOA.

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Calibration-Conditioned FiLM Decoders for Low-Latency Decoding of Quantum Error Correction Evaluated on IBM Repetition-Code Experiments

Real-time decoding of quantum error correction (QEC) is essential for enabling fault-tolerant quantum computation. A practical decoder must operate with high accuracy at low latency, while remaining robust to spatial and temporal variations in hardware noise. We introduce a hardware-conditioned neural decoder framework designed to exploit the natural separation of timescales in superconducting processors, where calibration drifts occur over hours while error correction requires microsecond-scale responses. By processing calibration data through a graph-based encoder and conditioning a lightweight convolutional backbone via feature-wise linear modulation (FiLM), we decouple the heavy processing of device statistics from the low-latency syndrome decoding. We evaluate this approach using the 1D repetition code as a testbed on IBM Fez, Kingston, and Pittsburgh processors, collecting over 2.7 million experimental shots spanning distances up to d = 11. We demonstrate that a single trained model generalizes to unseen qubit chains and new calibration data acquired days later without retraining. On these unseen experiments, the FiLM-conditioned decoder achieves up to an 11.1x reduction in logical error rate relative to modified minimum-weight perfect matching. We observe that by employing a network architecture that exploits the highly asynchronous nature of system calibration and decoding, hardware-conditioned neural decoding demonstrates promising, adaptive performance with negligible latency overhead relative to unconditioned baselines.

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FTCircuitBench: A Benchmark Suite for Fault-Tolerant Quantum Compilation and Architecture

Realizing large-scale quantum advantage is expected to require quantum error correction (QEC), making the compilation and optimization of logical operations a critical area of research. Logical computation imposes distinct constraints and operational paradigms that differ from those of the Noisy Intermediate-Scale Quantum (NISQ) regime, motivating the continued evolution of compilation tools. Given the complexity of this emerging stack, where factors such as gate decomposition precision and computational models must be co-designed, standardized benchmarks and toolkits are valuable for evaluating progress. To support this need, we introduce FTCircuitBench, which serves as: (1) a benchmark suite of impactful quantum algorithms, featuring pre-compiled instances in both Clifford+T and Pauli Based Computation models; (2) a modular end-to-end pipeline allowing users to compile and decompose algorithms for various fault-tolerant architectures, supporting both prebuilt and custom optimization passes; and (3) a toolkit for evaluating the impact of algorithms and optimization across the full compilation stack, providing detailed numerical analysis at each stage. FTCircuitBench is fully open-sourced and maintained on Github.

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Exact and Efficient Stabilizer Simulation of Thermal-Relaxation Noise for Quantum Error Correction

Stabilizer-based simulation of quantum error-correcting codes typically relies on the Pauli-twirling approximation (PTA) to render non-Clifford noise classically tractable, but PTA can distort the behavior of physically relevant channels such as thermal relaxation. Physically accurate noise simulation is needed to train decoders and understand the noise suppression capabilities of quantum error correction codes. In this work, we develop an exact and stabilizer-compatible model of qubit thermal relaxation noise and show that the combined amplitude damping and dephasing channel admits a fully positive probability decomposition into Clifford operations and reset whenever $T_2 \leqslant T_1$. For $T_2 > T_1$, the resulting decomposition is negative, but allows a smaller sampling overhead versus independent channels. We further introduce an approximated error channel with reset that removes the negativity of the decomposition while achieving higher channel fidelity to the true thermal relaxation than PTA, and extend our construction to finite temperature relaxation. We apply the exact combined model to investigate large surface codes and bivariate bicycle codes on superconducting platforms with realistic thermal relaxation error. The differing logical performances across code states further indicate that noise-model-informed decoders will be essential for accurately capturing thermal-noise structure in future fault-tolerant architectures.

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F2: Offline Reinforcement Learning for Hamiltonian Simulation via Free-Fermionic Subroutine Compilation

Compiling shallow and accurate quantum circuits for Hamiltonian simulation remains challenging due to hardware constraints and the combinatorial complexity of minimizing gate count and circuit depth. Existing optimization method pipelines rely on hand-engineered classical heuristics, which cannot learn input-dependent structure and therefore miss substantial opportunities for circuit reduction. We introduce F2, an offline reinforcement learning framework that exploits free-fermionic structure to efficiently compile Trotter-based Hamiltonian simulation circuits. F2 provides (i) a reinforcement-learning environment over classically simulatable free-fermionic subroutines, (ii) architectural and objective-level inductive biases that stabilize long-horizon value learning, and (iii) a reversible synthetic-trajectory generation mechanism that consistently yields abundant, guaranteed-successful offline data. Across benchmarks spanning lattice models, protein fragments, and crystalline materials (12-222 qubits), F2 reduces gate count by 47% and depth by 38% on average relative to strong baselines (Qiskit, Cirq/OpenFermion) while maintaining average errors of 10^(-7). These results show that aligning deep reinforcement learning with the algebraic structure of quantum dynamics enables substantial improvements in circuit synthesis, suggesting a promising direction for scalable, learning-based quantum compilation

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Characterizing QUBO Reformulations of the Max-k-Cut Problem for Quantum Computing

Quantum computing offers significant potential for solving NP-hard combinatorial (optimization) problems that are beyond the reach of classical computers. One way to tap into this potential is by reformulating combinatorial problems as a quadratic unconstrained binary optimization (QUBO) problem. The solution of the QUBO reformulation can then be addressed using adiabatic quantum computing devices or appropriate quantum computing algorithms on gate-based quantum computing devices. In general, QUBO reformulations of combinatorial problems can be readily obtained by properly penalizing the violation of the problem's constraints in the original problem's objective. However, characterizing tight (i.e., minimal but sufficient) penalty coefficients for this purpose is important and non-trivial for enabling the solution of the resulting QUBO in current and near-term quantum computing devices. Along these lines, we present closed-form characterizations of tight penalty coefficients for two distinct QUBO reformulations of the max $k$-cut problem whose values depend on the (weighted) degree of the vertices of the graph defining the problem. These findings contribute to the ongoing effort to make quantum computing a viable tool for solving combinatorial problems at scale. We support our theoretical results with illustrative examples and simple numerical results.

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Tableau-Based Framework for Efficient Logical Quantum Compilation

Quantum computing holds the promise of solving problems intractable for classical computers, but practical large-scale quantum computation requires error correction to protect against errors. Fault-tolerant quantum computing (FTQC) enables reliable execution of quantum algorithms, yet they often demand substantial physical qubit overhead. Resource-efficient FTQC architectures minimize the number of physical qubits required, saving more than half compared to other architectures, but impose constraints that introduce up to 4.7$\times$ higher runtime overhead. In this paper, we present TQC, a \underline{T}ableau-based \underline{Q}uantum \underline{C}ompiler framework that minimizes FTQC runtime overhead without requiring additional physical qubits. By leveraging operation reorderability and latency hiding through parallel execution, TQC reduces FTQC runtime overhead by \textbf{2.57$\times$} on average. Furthermore, FTQC circuits often contain millions of gates, leading to substantial compilation overhead. To address this, we optimize the core data structure, the tableau, used in stabilizer formalism. We provide two tailored versions of the Tableau data type, each designed for different usage scenarios. These optimizations yield an overall performance improvement of more than \textbf{1000$\times$} compared to state-of-the-art FTQC optimization tools.

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STABSim: A Parallelized Clifford Simulator with Features Beyond Direct Simulation

The quantum stabilizer formalism became foundational for understanding error correction soon after the realization of the first useful quantum error correction codes. Stabilizers provide a way to describe sets of quantum states which are valid codewords within a quantum error correction (QEC) scheme. Existing stabilizer simulators are single threaded applications used to sample larger codes than is possible with other methods. However, there is an outstanding gap in the scaling and accuracy of current simulators for QEC as quantum computing exceeds hundreds of qubits, along with an under-utilization of the capabilities of highly-efficient stabilizer simulation across other quantum domains. In this work, we present the first GPU-accelerated tableau stabilizer simulator to scale better than CPU methods in QEC workloads, by trivializing Clifford gates and exploiting the large parallelism of dedicated GPUs with CUDA warp-level primitives to quickly overcome costly measurement gates. We then implement a new error model that captures non-unitarity in T1/T2 error channels much faster and with exact accuracy for most physical qubits, demonstrate a chemistry use case, and present a new Clifford+T to Pauli-Based Computing (PBC) transpilation optimization through our simulator.

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Symbolic Hamiltonian Compiler for Hybrid Qubit-Boson Processors

Quantum simulation of the interactions of fermions and bosons -- the fundamental particles of nature -- is essential for modeling complex quantum systems in material science, chemistry and high-energy physics and has been proposed as a promising application of fermion-boson quantum computers, which overcome the overhead encountered in mapping fermions and bosons to qubits. However, compiling the simulation of specific fermion-boson Hamiltonians into the natively available fermion-boson gate set is challenging. In particular, the large local dimension of bosons renders matrix-based compilation methods, as used for qubits and in existing tools such as Bosonic Qiskit or OpenFermion, challenging. We overcome this issue by introducing a novel symbolic compiler based on matrix-free symbolic manipulation of second quantised Hamiltonians, which automates the decomposition of fermion-boson second quantized problems into qubit-boson instruction set architectures. This integration establishes a comprehensive pipeline for simulating quantum systems on emerging qubit-boson and fermion-boson hardware, paving the way for their large-scale usage.

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Hardware-aware Compilation for Chip-to-Chip Coupler-Connected Modular Quantum Systems

As quantum processors scale, monolithic architectures face growing challenges due to limited qubit density, heterogeneous error profiles, and restricted connectivity. Modular quantum systems, enabled by chip-to-chip coupler-connected modular architectures, provide a scalable alternative. However, existing quantum compilers fail to accommodate this new architecture. We introduce CCMap, a circuit-compiler co-design framework that enhances existing quantum compilers with system-level coordination across modular chips. It leverages calibration data and introduces a coupler-aligned and noise-aware cost metric to evaluate circuit compilation. CCMap integrates with existing compilers by partitioning circuits into subcircuits compiled on individual chips, followed by a global mapping step to minimize the total cost. We evaluated CCMap on IBM-Q noisy emulators using real hardware calibrations across various coupler-connected topologies. Results show that CCMap improves circuit fidelity by up to 21.9%, representing a 30% increase, and reduces compilation cost by up to 58.6% over state-of-the-art baselines. These findings highlight CCMap's potential to enable scalable, high-fidelity execution in coupler-connected modular quantum systems.

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SPARO: Surface-code Pauli-based Architectural Resource Optimization for Fault-tolerant Quantum Computing

Surface codes represent a leading approach for quantum error correction (QEC), offering a path towards universal fault-tolerant quantum computing (FTQC). However, efficiently implementing algorithms, particularly using Pauli-based computation (PBC) with lattice surgery, necessitates careful resource optimization. Prior work often employs static layouts and simplified error models. These typically fail to capture the full costs and dynamic nature of active computation, leading to resource bottlenecks and suboptimal architectural designs. To address this, we introduce SPARO. SPARO features a comprehensive logical error model based on a large corpus of numerical simulations encompassing active Pauli-based computation (PBC) operations-including Pauli product measurements (PPMs), idling qubits, and patch rotations. Our numerical models are integrated within an end-to-end compilation pipeline. SPARO analyzes algorithm-specific bottlenecks arising from constraints such as limited routing areas or magic-state factory throughput. SPARO then dynamically allocates available hardware resources, balancing compute, routing, and magic-state distillation, to minimize space-time overhead and logical error rates for specific workloads. Our simulations demonstrate that SPARO effectively identifies critical resource trade-offs. When evaluated on benchmark circuits, SPARO identifies resource configurations achieving up to 51.11% logical error rate reductions for 433-qubit ADDER circuits when compared to state-of-the-art static layouts using an identical total resource budget. This dynamic approach enables effective co-optimization of PBC execution and surface-code architectures, significantly improving overall resource efficiency. SPARO will be open sourced.

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Multi-Target Rydberg Gates via Spatial Blockade Engineering

Multi-target gates offer the potential to reduce gate depth in syndrome extraction for quantum error correction. Although neutral-atom quantum computers have demonstrated native multi-qubit gates, existing approaches that avoid additional control or multiple atomic species have been limited to single-target gates. We propose single-control-multi-target CZ^{\otimes N}) gates on a single-species neutral-atom platform that require no extra control and have gate durations comparable to standard CZ gates. Our approach leverages tailored interatomic distances to create an asymmetric blockade between the control and target atoms. Using a GPU-accelerated pulse synthesis protocol, we design smooth control pulses for CZZ and CZZZ gates, achieving fidelities of up to 99.55% and 99.24%, respectively, even in the presence of simulated atom placement errors and Rydberg-state decay. This work presents a practical path to implementing multi-target gates in neutral-atom systems, significantly reducing the resource overhead for syndrome extraction.

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Kernpiler: Compiler Optimization for Quantum Hamiltonian Simulation with Partial Trotterization

Quantum computing promises transformative impacts in simulating Hamiltonian dynamics, essential for studying physical systems inaccessible by classical computing. However, existing compilation techniques for Hamiltonian simulation, in particular the commonly used Trotter formulas struggle to provide gate counts feasible on current quantum computers for beyond-classical simulations. We propose partial Trotterization, where sets of non-commuting Hamiltonian terms are directly compiled allowing for less error per Trotter step and therefore a reduction of Trotter steps overall. Furthermore, a suite of novel optimizations are introduced which complement the new partial Trotterization technique, including reinforcement learning for complex unitary decompositions and high level Hamiltonian analysis for unitary reduction. We demonstrate with numerical simulations across spin and fermionic Hamiltonians that compared to state of the art methods such as Qiskit's Rustiq and Qiskit's Paulievolutiongate, our novel compiler presents up to 10x gate and depth count reductions.

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Transpiler-Architecture Co-Design to Curb Clifford Costs in Fault-Tolerant Quantum Computing

Quantum Error Correction (QEC) codes form the foundation of Fault-Tolerant Quantum Computing (FTQC) and predominantly use the Clifford+T gate set. Recently, Clifford operations have become the key performance bottleneck in implementing QEC. While state-of-the-art approaches like Pauli-Based Compilation (PBC) reduce Clifford overhead by transforming Clifford gates into Pauli measurements, they do so at the cost of gate-level parallelism, inflating circuit depth and execution times. To overcome these limitations, we introduce TACO, a Transpiler-Architecture Co-design framework that tackles the Clifford bottleneck through circuit and architectural optimization. TACO uses FTQC insights to guide hardware-aware Clifford gate elimination and circuit restructuring, and leverages the resulting optimized circuits to refine architectural design. TACO applies FTQC-specific transformations to aggressively reduce Clifford overhead from rotation synthesis and Toffoli decompositions, while preserving gate-level parallelism. The resulting architecture is optimized for the locality and data-movement patterns of these circuits, enabling high-throughput, resource-efficient execution. Our evaluation across diverse benchmarks shows that TACO achieves up to 21.9x (mean 4.4x) reduction in execution time compared to the state-of-the-art baseline.

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