arXiv subjects

Shubin Liu

Publications and source records attributed to Shubin Liu.

At least 37 records · Page 2Linked to original sources

arXiv2019

Prototype of the Readout Electronics for WCDA in LHAASO

In the Large High Altitude Air Shower Observatory (LHAASO), the Water Cherenkov Detector Array (WCDA) is one of the key parts. The WCDA consists of 3600 Photomultiplier Tubes (PMTs) scattered in a 90000 m2 area, and both high precision time and charge measurements are required over a large dynamic range from 1 to 4000 Photo Electrons (P.E.). To achieve time measurement precision better than 500 ps RMS, high quality clock distribution and automatic phase compensation are needed among the 400 Front End Electronics (FEE) modules. To simplify the readout electronics architecture, clock, data, and commands are transferred simultaneously over 400-meter fibers, while high speed data transfer interface is implemented based on TCP/IP protocol. Design and testing of the readout electronics prototype for WCDA is presented in this paper. Test results indicate that a charge resolution better than 10% RMS @ 1 P.E. and 1% RMS @ 4000 P.E., and a time resolution better than 300 ps RMS are successfully achieved over the whole dynamic range, beyond the application requirement.

physics.ins-det↗

arXiv2019

Precise Clock Synchronization in the Readout Electronics of WCDA in LHAASO

The Water Cherenkov Detector Array (WCDA) is one of the key parts in the Large High Altitude Air Shower Observatory (LHAASO). In the WCDA, 3600 Photomultiplier Tubes (PMTs) and the Front End Electronics (FEEs) are scattered within a 90000 m2 area, while a time measurement resolution better than 0.5 ns is required in the readout electronics. To achieve such time measurement precision, high quality clock distribution and synchronization among the 400 FEEs (each FEE for 9 PMTs readout) is required. To simplify the electronics system architecture, data, commands, and clock are transmitted simultaneously through fibers over a 400-meter distance between FEEs and the Clock and Data Transfer Modules (CDTMs). In this article, we propose a new method based on the White Rabbit (WR) to achieve completely automatic clock phase alignment between different FEEs. The original WR is enhanced to overcome the clock delay fluctuations due to ambient temperature variations. This paper presents the general scheme, the design of prototype electronics, and initial test results. These indicate that a clock synchronization precision better than 50 ps is achieved over 1 km fibers, which is well beyond the application requirement.

physics.ins-det↗

arXiv2019

Bunch-by-bunch Beam Transverse Feedback Electronics Designed for SSRF

Shanghai Synchrotron Radiation Facility (SSRF), is one of the third-generation high-beam current (3.5 GeV) synchrotron light sources. In the storage ring of SSRF, multi-bunch instabilities would increase beam emittance and energy spread, which degrade beam quality and even cause beam loss. To address the above issues, a Transverse Feedback System is indispensable for SSRF, in which the key component is the bunch-by-bunch transverse feedback electronics. The whole feedback system consists of five main parts: Beam Position Monitor (BPM), RF front-end, signal processor, RF amplifier, and vertical/horizontal transverse kickers. The dissertation focuses on the signal processor we design, which is the main part of the feedback electronics. We conducted initial testing on the signal processor to evaluate its performance and function. Test results indicate that ENOB of the Analog-to-Digital Conversion circuit is better than 10 bit with 100 MHz input signal, and remains better than 9.5 bit up to 300 MHz, which is good enough for the required 7.9 bit; the frequency response of the whole system also concords well with the simulation results, and the suppression in amplitude response at the critical frequency points is better 35 dB while the uncertainty of phase response is better than 2 degree, all meeting the application requirement.

physics.ins-det↗

arXiv2019

Prototype of a front-end readout ASIC designed for the Water Cherenkov Detector Array in LHAASO

The Large High Altitude Air Shower Observatory is in the R&D phase, in which the Water Cherenkov Detector Array is an important part. The signals of Photo-Multiplier Tubes would vary from single photo electron to 4000 photo electrons, and both high precision charge and time measurement is required. To simplify the signal processing chain, the charge-to-time conversion method is employed. A prototype of the front-end readout ASIC is designed and fabricated in Chartered 0.35 μm CMOS technology, which integrates time disctrimination and converts the input charge information to pulse widths. With Time-to-Digital Converters, both time and charge can be digitized at the same time. We have conducted initial tests on this chip, and the results indicate that a time resolution better than 0.5 ns is achieved over the full dynamic range (1~ 4000 photo electrons, corresponding to 0.75 ~ 3000 pC with the threshold of 0.188 pC); the charge resolution is better than 1% with large input amplitudes (500 ~ 4000 photo electrons), and remains better than 15% with a 1 photo electron input amplitude, which is beyond the application requirement.

physics.ins-det↗

arXiv2019

Research of time discrimination circuits for PMT signal readout over large dynamic range in LHAASO WCDA

In the readout electronics of the Water Cerenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO), both high-resolution charge and time measurement are required over a dynamic range from 1 photoelectron (P.E.) to 4000 P.E. for the PMT signal readout. In this paper, we present our work on the design of time discrimination circuits in LHAASO WCDA, especially on improvement to reduce the circuit dead time. Several approaches were studied through analysis and simulations, and actual circuits were designed and tested in the laboratory to evaluate the performance. Test results indicate that a time resolution better than 500 ps RMS is achieved in the whole large dynamic range, and the circuit dead time is successfully reduced to less than 200 ns.

physics.ins-det↗

arXiv2019

Data and clock transmission interface for the WCDA in LHAASO

The Water Cherenkov Detector Array (WCDA) is one of the major components of the Large High Altitude Air Shower Observatory (LHAASO). In the WCDA, 3600 Photomultiplier Tubes (PMTs) and the Front End Electronics (FEEs) are scattered over a 90000 m2 area, while high precision time measurements (0.5 ns RMS) are required in the readout electronics. To meet this requirement, the clock has to be distributed to the FEEs with high precision. Due to the "triggerless" architecture, high speed data transfer is required based on the TCP/IP protocol. To simplify the readout electronics architecture and be consistent with the whole LHAASO readout electronics, the White Rabbit (WR) switches are used to transfer clock, data, and commands via a single fiber of about 400 meters. In this paper, a prototype of data and clock transmission interface for LHAASO WCDA is developed. The performance tests are conducted and the results indicate that the clock synchronization precision of the data and clock transmission is better than 50 ps. The data transmission throughput can reach 400 Mbps for one FEE board and 180 Mbps for 4 FEE boards sharing one up link port in WR switch, which is better than the requirement of the LHAASO WCDA.

physics.ins-det↗

arXiv2019

Prototype of a transient waveform recording ASIC

The paper presents the design and measurement results of a transient waveform recording ASIC based on the Switched Capacitor Array (SCA) architecture. This 0.18 μm CMOS prototype device contains two channels and each channel employs a SCA of 128 samples deep, a 12-bit Wilkinson ADC and a serial data readout. A series of tests have been conducted and the results indicate that: a full 1 V signal voltage range is available, the input analog bandwidth is approximately 450 MHz and the sampling speed is adjustable from 0.076 to 3.2 Gsps (Gigabit Samples Per Second). For precision waveform timing extraction, careful calibration of timing intervals between samples is conducted to improve the timing resolution of such chips, and the timing precision of this ASIC is proved to be better than 15 ps RMS.

physics.ins-det↗

arXiv2019

Design and testing of a bunch-by-bunch beam position transverse feedback processor

Shanghai Synchrotron Radiation Facility (SSRF) is a 3.5 GeV storage ring with a bunch rate of 499.654 MHz, harmonic number of 720, and circumference of 432 meters. SSRF injection works at 3.5 GeV, where the multi-bunch instabilities limit the maximum stored current. In order to suppress multi-bunch instabilities caused by transverse impedance, a bunch-by-bunch transverse feedback system is indispensable for SSRF. The key component of that system is the bunch-by-bunch transverse feedback electronics. An important task in the electronics is precise time synchronization. In this paper, a novel clock synchronization and precise delay adjustment method based on the PLLs and delay lines are proposed. Test results indicate that the ENOB (Effective Number Of Bits) of the analog-to-digital conversion circuit is better than 9 bits in the input signal frequency range from 100 kHz to 700 MHz, and the closed loop attenuation at the critical frequency points is better than 40 dB. The initial commissioning tests with the beam in SSRF are also conducted, and the results are consistent with the expectations.

physics.ins-det↗

arXiv2019

An overdetermined linear equations-based time calibration method for fast sampling ASICs

A novel time calibration method for waveform sampling application specific integrated circuits (ASICs) based on switched capacitor arrays (SCAs) is proposed in this paper. Precision timing extraction using SCA ASICs has been proved to be a promising technique in many high energy physics experiments. However, such ASICs suffer from irregular sampling intervals caused by process variations. Therefore, careful calibration is required to improve the time resolution of such systems. We evaluated the limitation of a popular method using the proportionality between voltage amplitude and sampling interval of adjacent switched-capacitor cells responding to either a sawtooth wave or a sine wave. The new time calibration method presented here utilizes the relationship between sampling intervals and the known input signal period to establish overdetermined linear equations, and the roots of these equations correspond to the actual sampling intervals. We applied this new method to a pulse timing test with an ASIC designed by our team, and the test results indicate that the new time calibration method is effective.

physics.ins-det↗

arXiv2019

Calibration and Status of the 3D Imaging Calorimeter of DAMPE for Cosmic Ray Physics on Orbit

The DArk Matter Particle Explorer (DAMPE) developed in China was designed to search for evidence of dark matter particles by observing primary cosmic rays and gamma rays in the energy range from 5 GeV to 10 TeV. Since its launch in December 2015, a large quantity of data has been recorded. With the data set acquired during more than a year of operation in space, a precise time-dependent calibration for the energy measured by the BGO ECAL has been developed. In this report, the instrumentation and development of the BGO Electromagnetic Calorimeter (BGO ECAL) are briefly described. The calibration on orbit, including that of the pedestal, attenuation length, minimum ionizing particle peak, and dynode ratio, is discussed, and additional details about the calibration methods and performance in space are presented.

astro-ph.IM↗

arXiv2018

Readout Electronics for CEPC Semi-Digital Hadron Calorimeter Pre-prototype

CEPC (Circular Electron and Positron Collider) is a large experiment facility proposed by Chinese particle physics community. One of its running option is being the Higgs factory. Calorimeter is the main part of this experiment to measure the jet energy. Semi-digital hadron calorimeter (SDHCAL) is one of the options for the hadron measurement. GEM detector with its high position resolution and flexible configuration is one of the candidates for the active layer of the SDHCAL. The main purpose of this paper is to provide a feasible readout method for the GEM-based semi-digital hadron calorimeter. A small-scale prototype is designed and implemented, including front-end board (FEB) and data interface board (DIF). The prototype electronics has been tested. The equivalent RMS noise of all channels is below 0.35fC. The dynamic range is up to 500fC and the gain variation is less than 1%. The readout electronics is applied on a double-layer GEM detector with 1cm*1cm readout pad. Result indicates that the electronics works well with the detector. The detection efficiency of MIP is over 95% with 5fC threshold.

physics.ins-det↗

arXiv2018

Development of the Front-End Electronics for PandaX-III Prototype TPC

The Particle And Astrophysical Xenon Experiment III (PandaX-III) is an experiment to search for the Neutrinoless Double Beta Decay (NLDBD) using 200 kg radio-pure high-pressure gaseous xenon TPC with Micromegas detectors at both ends and cathode in the middle. A small-scale TPC equipped with 7 Microbulk Micromegas detectors is developed as the prototype detector. 128 channels are readout following an X-Y design with strips of 3 mm pitch (64 channels each direction) from one Micromegas module. Highly integrated front-end electronics composed of 4 front-end cards with 1024 readout channels is designed to readout the charge of Micromegas anode signals, digitize the waveform after shaping and send compressed data to the DCM board. The cornerstone of the front-end electronics is a 64-channel application specific integrated circuit which is based on a switched capacitor array. The integral nonlinearity of the front-end electronics is less than 1% with 1 pC. The noise (RMS) of each readout channel is less than 0.9 fC with 1 microsecond peaking time and 1 pC range. Using the radioactive sources 56 Fe and 137 Cs, joint-tests of front-end electronics with the prototype TPC were carried out and the hit map of 7 Micromegas has been reconstructed.

physics.ins-det↗

arXiv2018

Prototype of Front-end Electronics for PandaX-4ton Experiment

At the China Jinping Underground Laboratory, the Particle AND Astrophysical Xenon phase IV (PandaX-4ton) in planning is a dark matter direct detection experiment with dual-phase xenon detector as an upgrade of the second phase of the experiment, PandaX-II. In this paper, the prototype of the front-end electronics of PandaX-4ton is presented. The front-end electronics consist of the high-gain preamplifier cards and the eight-channel digitizers with 14-bit resolution and 1 GSps sampling rate for waveform digitization. The clock synchronization circuit within the digitizer is well-designed to align all the PMT channels. The digitizer also contains gigabit fiber to exchange data with trigger and data acquisition system. The specification of effective number of bits f the digitizer is about 9.7 b at 148 MHz, and the integral nonlinearity of the digitizer ranges from -4 least significant bit (LSB) to +4 LSB, and the differential nonlinearity ranges from -0.6 LSB to +0.6 LSB. The performance of the front-end electronics can meet the requirements for the PandaX-4ton.

physics.ins-det↗

arXiv2018

Design of a Programmable Gain Waveform Digitization Instrument for Detector Calibration

To test and calibrate various detectors in nuclear and high energy physics experiments, a general purposed calibration instrument has been developed. All information including timing, amplitude and charge of signals can be directly obtained to calibrate detector with this instrument by amplifying and digitizing the signal waveform. The system consists of two parts, a large dynamic range pre-amplifier module and a high speed and high-resolution digitization module. The pre-amplifier module based on programmable gain amplifier and attenuator achieves gain from -26.2 dB to 24.4 dB, making it suitable to adapt to different detectors. Taking advantage of high speed and high-resolution analog-to-digit converter (ADC), the waveform digitization module samples the signal after conditioning with 12 bits resolution and up to 3.6 giga hertz samples per second (GSPS). To evaluate the feature of this instrument, an electronics testbench platform was installed and test results showed a bandwidth from direct current (DC) to 450 MHz and the effective number of bits (ENOB) is above 7 bits in high gain set and 5.8 bits in low gain set in the bandwidth range, which indicated that it had broad application prospect in detector calibration.

physics.ins-det↗

arXiv2018

A Design of FPGA Based Small Animal PET Real Time Digital Signal Processing and Correction Logic

Small animal Positron Emission Tomography (PET) is dedicated to small animal imaging. Animals used in experiments, such as rats and monkeys, are often much smaller than human bodies, which requires higher position and energy precision of the PET imaging system. Besides, Flexibility, high efficiency are also the major demands of a practical PET system. These requires a high-quality analog front-end and a digital signal processing logic with high efficiency and compatibility of multiple data processing modes. The digital signal processing logic of the small animal PET system presented in this paper implements 32-channel signal processing in a single Xilinx Artix-7 family of Field-Programmable Gate Array (FPGA). The logic is designed to support three online modes which are regular package mode, flood map and energy spectrum histogram. Several functions are integrated, including two-dimensional (2D) raw position calculation, crystal identification, events filtering, etc. Besides, a series of online corrections are also integrated, such as photon peak correction to 511 keV and timing offset correction with crystal granularity. A Gigabit Ethernet interface is utilized for data transfer, Look-Up Tables (LUTs) configuration and commands issuing. The pipe-line logic processes the signals at 125 MHz with a rate of 1,000,000 events/s. A series of initial tests are conducted. The results indicate that the digital processing logic achieves the expectations.

eess.SP↗

arXiv2018

A New All-Digital Background Calibration Technique for Time-Interleaved ADC Using First Order Approximation FIR Filters

This paper describes a new all-digital technique for calibration of the mismatches in time-interleaved analog-to-digital converters (TIADCs) to reduce the circuit area. The proposed technique gives the first order approximation of the gain mismatches and sample-time mismatches, and employs first order approximation FIR filter banks to calibrate the sampled signal, which do not need large number of FIR taps. In the case of a two-channel 12-bit TIADC, the proposed technique improves SINAD of simulated data from 45dB to 69dB, and improves SINAD of measured data from 47dB to 53dB, while the number of FIR taps is only 30. In the case of slight mismatches, 24-bit FIR coefficient is sufficient to correct 12-bit signals, which makes it easy to implement this technique in hardware. In addition, this technique is not limited by the number of sub-ADC channels and can be calculated in parallel in hardware, these features enable this technique to be versatile and capable of real-time calibration.

eess.SP↗

arXiv2018

Testing of Front-End Readout Prototype ASICs Designed for WCDA in LHAASO

The water Cherenkov detector array (WCDA) is one of the key detectors in the large high altitude air shower observatory (LHAASO), which is proposed for very high gamma ray source survey. In WCDA, there are more than 3000 photomultiplier tubes (PMTs) scattered under water in an area of 80000 m2. As for the WCDA readout electronics, both high precision time and charge measurement is required over a large dynamic range from 1 photon electron (P.E.) to 4000 P.E. To reduce the electronics complexity and improve the system reliability, a readout scheme based on application specific integrated circuits (ASICs) is proposed. Two prototype ASICs were designed and tested. The first ASIC integrates amplification and shaping circuits for charge measurement and discrimination circuits used for time measurement. The shaped signal is further fed to the second ADC ASIC, while the output signal from the discriminator is digitized by the FPGA-based time-to-digital converter (TDC). Test results indicate that time resolution is better than 250 ps RMS, and the charge resolution is better than 10% at 1 P.E., and 1% at 4000 P.E. which meets the requirements of the LHAASO WCDA.

physics.ins-det↗

arXiv2018

High-speed RF Switch Electronics for picking up of Electron-Positron Beam Bunches

Beam diagnostics is important to guarantee good quality of beam in particle accelerator. Both the electron and positron run in the tunnel in some modern electron positron colliders such as Circular Electron Positron Collider (CEPC) to be built and Beijing Electron Positron Collider II (BEPC II). To measure the electron and positron beams, picking up of these two different bunches in real time is of notable concern. Because the time interval between adjacent electron and positron bunches is quite small, for example, 6 ns in CEPC, high-speed switch electronics is required. This paper presents the prototype design of a high-speed radio frequency (RF) electronics that can pick up nanosecond positron-electron beam bunches with a switching time of less than 6 ns. Fast separation of electron and positron is achieved based on RF switches and precise delay adjustment of the controlling signals (~10 ps). Initial tests have been conducted in the laboratory to evaluate the performance of electronics, the results indicate that this circuit can successfully pick up the bunch signal within a time interval of 6 ns, which makes it possible to further measure the electron and position beams simultaneously.

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