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Shubin Liu

Publications and source records attributed to Shubin Liu.

At least 55 records · Page 3Linked to original sources

Development of a 256-channel Time-of-flight Electronics System For Neutron Beam Profiling

A 256-channel time-of-flight (TOF) electronics system has been developed for a beam line facility called "Back-n WNS" in China Spallation Neutron Source (CSNS). This paper shows the structure and performance of electronics system and the test results in CSNS. A 256-channel photomultiplier tube (PMT) is chosen as the detector in this system. In order to acquire the time information from the PMT, an electronics system has been designed. The electronics system mainly includes one front-end board (FEB), four time-to-digital converter (TDC) boards and one clock distribution module (CDM). There are 256 channels on FEB and 64 channels on each TDC board. The FEB is connected to the PMT with high-density connectors and the TDC boards are connected to the FEB through 2m cables. The TDC boards are 6U size so that they can be PCI extensions for Instrumentation (PXI) cards. Data from TDC boards can be transferred to the PXI control card through the backboard. In order to make four TDC boards work synchronously, a CDM outputs four clock signals to TDC boards which are distributed from one clock source. The TDC boards achieve a timing resolution of 3.5ns by test with a signal generator. The TOF measurement system has been used in CSNS.

physics.ins-det↗

Study on the Real-time Lossless Data Compression Method Used in the Readout System for Micro-pattern Gas Detector

The data compression technology now is fully developed and widely used in many fields such as communication, multi-media, image information processing and so on. The large physical experiments, especially the ones with Micro-pattern Gas Detectors (MPGD), which always have many readout channels and have a lot of data to be transferred and saved, are however relatively seldom use this technology. In this paper, the real-time lossless data compression method is proposed for a general-purposed MPGD readout system. The lossless data compression can reduce the data transmission bandwidth of the system as well as keep all information of the data. The compression method discussed in the paper mainly consists of two steps. The first step is to pre-process the data according to different characteristics of different signals and the second step is to compress the pre-processed data using common lossless compression algorithm. Besides, the whole compression method is implemented in the Field-Programmable Gate Array (FPGA) and able to run real-timely. The system is then used to readout two different kinds of signals and the compression rate can reach as high as 43% and 30% respectively.

physics.ins-det↗

Application of FPGA Acceleration in ADC Performance Calibration

In recent years, high speed and high resolution analog-to-digital converter (ADC) is widely employed in many physical experiments, especially in high precision time and charge measurement. The rapid increasing amount of digitized data demands faster computing. FPGA acceleration has an attracting prospect in data process for its stream process and parallel process feature. In this paper, an ADC performance calibration application based on FPGA acceleration is described. FPGA reads the ADC digitized data stream from PC memory, processes and then writes processed result back to the PC memory. PCIE bus is applied to increase the data transfer speed, and floating point algorithm is applied to improve the accuracy. The test result shows that FPGA acceleration can reduce the processing time of the ADC performance calibration compared with traditional method of C-based CPU processing. This frame of PCIE-based FPGA acceleration method can be applied in analysis and simulation in the future physical experiment for large ADC array, such as CCD camera and waveform digitization readout electronics calibration.

eess.SP↗

PandaX-III: Searching for Neutrinoless Double Beta Decay with High Pressure $^{136}$Xe Gas Time Projection Chambers

Searching for the Neutrinoless Double Beta Decay (NLDBD) is now regarded as the topmost promising technique to explore the nature of neutrinos after the discovery of neutrino masses in oscillation experiments. PandaX-III (Particle And Astrophysical Xenon Experiment III) will search for the NLDBD of $^{136}$Xe at the China Jin Ping underground Laboratory (CJPL). In the first phase of the experiment, a high pressure gas Time Projection Chamber (TPC) will contain 200 kg, 90% $^{136}$Xe enriched gas operated at 10 bar. Fine pitch micro-pattern gas detector (Microbulk Micromegas) will be used at both ends of the TPC for the charge readout with a cathode in the middle. Charge signals can be used to reconstruct tracks of NLDBD events and provide good energy and spatial resolution. The detector will be immersed in a large water tank to ensure $\sim$5 m of water shielding in all directions. The second phase, a ton-scale experiment, will consist of five TPCs in the same water tank, with improved energy resolution and better control over backgrounds.

physics.ins-det↗

Fast Control Latency Uncertainty Elimination for the BESIII ETOF Upgrade

A new fanning topology is proposed to precisely fan out fast control signals in the Beijing Spectrometer (BES III) end-cap time-of-flight (ETOF) electronics. However, uncertainty in transfer latency is introduced by the new fanning channel, which will degrade the precision of fast control. In this paper, latency uncertainty elimination for the BESIII ETOF upgrade is introduced. The latency uncertainty is determined by a Time-Digital-Converter (TDC) embedded in a Field-Programmable Gate Array (FPGA) and is eliminated by re-capturing at synchronous and determinate time. Compared with the existing method of Barrel-cap TOF (BTOF), it has advantages of flexible structure, easy calibration and good adaptability. Field tests on the BES III ETOF system show that this method effectively eliminates transfer latency uncertainty.

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First results of the new endcap TOF commissioning at BESIII

The upgrade of the current BESIII Endcap TOF (ETOF) is carried out with the Multi-gap Resistive Plate Chamber (MRPC) technology. The installation of the new ETOF has been finished in October 2015. The first results of the MRPCs commissioning at BESIII are reported in this paper.

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Temperature Dependence Calibration and Correction of the DAMPE BGO Electromagnetic Calorimeter

A BGO electromagnetic calorimeter (ECAL) is built for the DArk Matter Particle Explorer (DAMPE) mission. The effect of temperature on the BGO ECAL was investigated with a thermal vacuum experiment. The light output of a BGO crystal depends on temperature significantly. The temperature coefficient of each BGO crystal bar has been calibrated, and a correction method is also presented in this paper.

physics.ins-det↗

The calibration and electron energy reconstruction of the BGO ECAL of the DAMPE detector

The DArk Matter Particle Explorer (DAMPE) is a space experiment designed to search for dark matter indirectly by measuring the spectra of photons, electrons, and positrons up to 10 TeV. The BGO electromagnetic calorimeter (ECAL) is its main sub-detector for energy measurement. In this paper, the instrumentation and development of the BGO ECAL is briefly described. The calibration on the ground, including the pedestal, minimum ionizing particle (MIP) peak, dynode ratio, and attenuation length with the cosmic rays and beam particles is discussed in detail. Also, the energy reconstruction results of the electrons from the beam test are presented.

physics.ins-det↗

An Analogue Front-End ASIC Prototype Designed For PMT Signal Readout

The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated in Chartered 0.35 μm CMOS technology is designed to read out PMT signal in the WCDA. This ASIC employs leading edge discrimination and RC4 shaping structure; combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E. and better than 1% with large input signals (300 P.E. to 4000 P.E.). Besides, this ASIC has a small channel-to-channel crosstalk and low ambient temperature dependency.

physics.ins-det↗

Application of Real-time Digitization Technique in Beam Measurement for Accelerators

Beam measurement is very important for accelerators. With the development of analog-to-digital conversion techniques, digital beam measurement becomes a research hot spot. IQ (In-phase & Quadrature-phase) analysis based method is an important beam measurement approach, the principle of which is presented and discussed in this paper. The State Key Laboratory of Particle Detection and Electronics in University of Science and Technology of China has devoted efforts to the research of digital beam measurement based on high-speed high-resolution analog-to-digital conversion, and a series of beam measurement instruments were designed for China Spallation Neutron Source (CSNS), Shanghai Synchrotron Radiation Facility (SSRF), and Accelerator Driven Sub-critical system (ADS).

physics.acc-ph↗

Evaluation of a front-end ASIC for the readout of PMTs in large dynamic range

The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 μm CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @ 1 Photo Electron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

physics.ins-det↗

TOT Measurement Implemented in FPGA TDC

Time measurement plays a crucial rule for the purpose of particle identification in high energy physical experiments. With the upgrading of physical goal and the developing of electronics, modern time measurement system meets the requirement of excellent resolution specification as well as high integrity. Due to Field Programmable Gate Array (FPGA), FPGA time-to-digital converter (TDC) becomes one of mature and prominent time measurement methods in recent years. For correcting time-walk effect caused by leading timing, time-over-threshold (TOT) measurement should be added in the FPGA TDC. TOT can be obtained by measuring the interval time of signal leading and trailing edge. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels can be used at the same time, one for leading, the other for trailing. However, this method will increase the amount of used FPGA resource and reduce the TDC's integrity unavoidably. This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method, TOT measure can be achieved in only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Test shows that this TDC can achieve resolution better than 15 ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measuring dead time is about 2 clock cycles, which makes it be good for applications of higher physical event rate

physics.ins-det↗

Waveform Timing Performance of a 5 GS/s Fast Pulse Sampling Module with DRS4

We first clarify timing issues of non-uniform sampling intervals regarding a 5 GS/s fast pulse sampling module with DRS4. Calibration strategy is proposed, and as a result, the waveform timing performance is improved to be below 10 ps RMS. We then further evaluate waveform timing performance of the module by comparing with a 10 GS/s oscilloscope in a setup with plastic scintillators and fast PMTs. Different waveform timing algorithms are employed for analysis, and the module shows comparable timing performance with that of the oscilloscope.

physics.ins-det↗

Design of the Readout Electronics for the Qualification Model of DAMPE BGO Calorimeter

The DAMPE (DArk Matter Particle Explorer) is a scientific satellite being developed in China, aimed at cosmic ray study, gamma ray astronomy, and searching for the clue of dark matter particles, with a planned mission period of more than 3 years and an orbit altitude of about 500 km. The BGO Calorimeter, which consists of 308 BGO (Bismuth Germanate Oxid) crystal bars, 616 PMTs (photomultiplier tubes) and 1848 dynode signals, has approximately 32 radiation lengths. It is a crucial sub-detector of the DAMPE payload, with the functions of precisely measuring the energy of cosmic particles from 5 GeV to 10TeV, distinguishing positrons/electrons and gamma rays from hadron background, and providing trigger information for the whole DAMPE payload. The dynamic range for a single BGO crystal is about 2?105 and there are 1848 detector signals in total. To build such an instrument in space, the major design challenges for the readout electronics come from the large dynamic range, the high integrity inside the very compact structure, the strict power supply budget and the long term reliability to survive the hush environment during launch and in orbit. Currently the DAMPE mission is in the end of QM (Qualification Model) stage. This paper presents a detailed description of the readout electronics for the BGO calorimeter.

astro-ph.IM↗

Study on FPGA SEU Mitigation for Readout Electronics of DAMPE BGO Calorimeter

The BGO calorimeter, which provides a wide measurement range of the primary cosmic ray spectrum, is a key sub-detector of Dark Matter Particle Explorer (DAMPE). The readout electronics of calorimeter consists of 16 pieces of Actel ProASIC Plus FLASH-based FPGA, of which the design-level flip-flops and embedded block RAMs are single event upset (SEU) sensitive in the harsh space environment. Therefore to comply with radiation hardness assurance (RHA), SEU mitigation methods, including partial triple modular redundancy (TMR), CRC checksum, and multi-domain reset are analyzed and tested by the heavy-ion beam test. Composed of multi-level redundancy, a FPGA design with the characteristics of SEU tolerance and low resource consumption is implemented for the readout electronics.

physics.ins-det↗

A Compact PCI-based Measurement and Control System for Satellite-Ground Quantum Communication

Since the 1990s, there has been a dramatic interest in quantum communication. Free-space quantum communication is being developed to ultra-long distance quantum experiment, which requires higher electronics performance, such as time measurement precision, data-transfer rate, and system integration density. As part of the ground station of quantum experiment satellite that will be launched in 2016, we specifically designed a compact PCI-based multi-channel electronics system with high time-resolution, high data-transfer-rate. The electronics performance of this system was tested. The time bin size is 23.9ps and the time precision root-mean-square (RMS) is less than 24ps for 16 channels. The dead time is 30ns. The data transfer rate to local computer is up to 35 MBps, and the count rate is up to 30M/s. The system has been proven to perform well and operate stably through a test of free space quantum key distribution (QKD) experiment.

quant-ph↗

A Multi-chain Measurements Averaging TDC Implemented in a 40 nm FPGA

A high precision and high resolution time-to-digital converter (TDC) implemented in a 40 nm fabrication process Virtex-6 FPGA is presented in this paper. The multi-chain measurements averaging architecture is used to overcome the resolution limitation determined by intrinsic cell delay of the plain single tapped-delay chain. The resolution and precision are both improved with this architecture. In such a TDC, the input signal is connected to multiple tapped-delay chains simultaneously (the chain number is M), and there is a fixed delay cell between every two adjacent chains. Each tapped-delay chain is just a plain TDC and should generate a TDC time for a hit input signal, so totally M TDC time values should be got for a hit signal. After averaging, the final TDC time is obtained. A TDC with 3 ps resolution (i.e. bin size) and 6.5 ps precision (i.e. RMS) has been implemented using 8 parallel tapped-delay chains. Meanwhile the plain TDC with single tapped-delay chain yields 24 ps resolution and 18 ps precision.

physics.ins-det↗

Development of COTS ADC SEE Test System for the ATLAS LAr Calorimeter Upgrade

Radiation-tolerant, high speed, high density and low power commercial off-the-shelf (COTS) analog-to-digital converters (ADCs) are planned to be used in the upgrade to the Liquid Argon (LAr) calorimeter front end (FE) trigger readout electronics. Total ionization dose (TID) and single event effect (SEE) are two important radiation effects which need to be characterized on COTS ADCs. In our initial TID test, Texas Instruments (TI) ADS5272 was identified to be the top performer after screening a total 17 COTS ADCs from different manufacturers with dynamic range and sampling rate meeting the requirements of the FE electronics. Another interesting feature of ADS5272 is its 6.5 clock cycles latency, which is the shortest among the 17 candidates. Based on the TID performance, we have designed a SEE evaluation system for ADS5272, which allows us to further assess its radiation tolerance. In this paper, we present a detailed design of ADS5272 SEE evaluation system and show the effectiveness of this system while evaluating ADS5272 SEE characteristics in multiple irradiation tests. According to TID and SEE test results, ADS5272 was chosen to be implemented in the full-size LAr Trigger Digitizer Board (LTDB) demonstrator, which will be installed on ATLAS calorimeter during the 2014 Long Shutdown 1 (LS1).

physics.ins-det↗