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Stefan Slesazeck

Publications and source records attributed to Stefan Slesazeck.

At least 19 recordsLinked to original sources

Peak splitting and bias fields in ferroelectric hafnia mediated by interface charge effects

The pristine state of hafnium based ferroelectric devices exhibits various unwanted properties, such as imprint and peak splitting, which diminish with bipolar cycling. The incorporation of a niobium oxide layer at different positions in metal-ferroelectric-metal and metal-ferroelectric-insulator-metal stacks is used to modify the pristine state of the device. X-ray photoelectron spectroscopy and transmission electron microscopy measurements are used to investigate the influence of niobium oxide on the zirconium hafnium oxide layer. It is hypothesized that the charged vacancies generated by the introduced niobium oxide in the adjacent zirconium hafnium oxide layer result in an electric bias field that influences the pristine polarization state of the domains. A comparison of different stacks shows that peak splitting in the pristine state is most likely related to the formation of opposing electric bias fields in upwards and downwards polarized domains. Furthermore, the incorporation of niobium oxide in the zirconium hafnium oxide/aluminum oxide capacitor stack in between the ferroelectric and insulating layer leads to a peak splitting free device without imprint, which could be explained by the increased influence of charge trapping near the zirconium hafnium oxide-/niobium oxide and niobium oxide-/aluminum oxide interfaces.

cond-mat.mtrl-sci

Weight update in ferroelectric memristors with identical and non-identical pulses

Ferroelectric tunnel junctions (FTJs) are a class of memristor which promise low-power, scalable, field-driven analog operation. In order to harness their full potential, operation with identical pulses is targeted. In this paper, several weight update schemes for FTJs are investigated, using either non-identical or identical pulses, and with time delays between the pulses ranging from 1 us to 10 s. Experimentally, a method for achieving non-linear weight update with identical pulses at long programming delays is demonstrated by limiting the switching current via a series resistor. Simulations show that this concept can be expanded to achieve weight update in a 1T1C cell by limiting the switching current through a transistor operating in sub-threshold or saturation mode. This leads to a maximum linearity in the weight update of 86% for a dynamic range (maximum switched polarization) of 30 μC/cm2. It is further demonstrated via simulation that engineering the device to achieve a narrower switching peak increases the linearity in scaled devices to >93 % for the same range.

cond-mat.mtrl-sci

Roadmap to Neuromorphic Computing with Emerging Technologies

The roadmap is organized into several thematic sections, outlining current computing challenges, discussing the neuromorphic computing approach, analyzing mature and currently utilized technologies, providing an overview of emerging technologies, addressing material challenges, exploring novel computing concepts, and finally examining the maturity level of emerging technologies while determining the next essential steps for their advancement.

eess.SP

A multi-pulse wakeup scheme for on-chip operation of devices based on ferroelectric doped HfO2 thin films

A wakeup scheme for ferroelectric thin Hf$_{0.5}$Zr$_{0.5}$O$_2$ films is presented, based on a gradual switching approach using multiple short pulses with a voltage amplitude roughly equal to the coercive voltage. This enables the on-chip wakeup and switching operation of ferroelectric devices such as tunnel junctions (FTJs) with identical pulses. After wakeup using alternating pulse trains which gradually switch the film polarization, FTJ operation is demonstrated to be as effective as after `normal' wakeup, with bipolar pulses of an amplitude larger than the coercive voltage. In this case the voltage applied during wakeup was reduced by 26\%, thereby lowering the required operating power.

physics.app-ph

Towards Non-Volatile Spin Orbit Devices: Deposition of Ferroelectric Hafnia on Monolayer Graphene/Co/HM Stacks

Although technologically challenging, the integration of ferroelectric thin films with graphene spintronics potentially allows the realization of highly efficient, electrically tuneable, non-volatile memories. Here, the atomic layer deposition (ALD) of ferroelectric Hf$_{0.5}$Zr$_{0.5}$O$_2$ (HZO) directly on graphene (Gr)/Co/heavy metal (HM) epitaxial stacks is investigated via the implementation of several nucleation methods. With an in-situ method employing an Al$_2$O$_3$ layer, the HZO demonstrates a remanent polarization (2Pr) of 19.2 $μC/cm^2$. An ex-situ, naturally oxidized sputtered Ta layer for nucleation produces a film with 2Pr of 10.81 $μC/cm^2$, but a lower coercive field over the stack and switching enduring over subsequent cycles. Magnetic hysteresis measurements taken before and after ALD deposition show strong perpendicular magnetic anisotropy (PMA), with only slight deviations in the magnetic coercive fields due to the HZO deposition process, thus pointing to a good preservation of the single-layer Gr. X-ray diffraction measurements further confirm that the high-quality interfaces demonstrated in the stack remain unperturbed by the ferroelectric deposition and anneal.

cond-mat.mtrl-sci

A Ferroelectric Tunnel Junction-based Integrate-and-Fire Neuron

Event-based neuromorphic systems provide a low-power solution by using artificial neurons and synapses to process data asynchronously in the form of spikes. Ferroelectric Tunnel Junctions (FTJs) are ultra low-power memory devices and are well-suited to be integrated in these systems. Here, we present a hybrid FTJ-CMOS Integrate-and-Fire neuron which constitutes a fundamental building block for new-generation neuromorphic networks for edge computing. We demonstrate electrically tunable neural dynamics achievable by tuning the switching of the FTJ device.

cs.ET

Improvement of FTJ on-current by work function engineering for massive parallel neuromorphic computing

HfO2-based ferroelectric tunnel junctions (FTJs) exhibit attractive properties for adoption in neuromorphic applications. The combination of ultra-low-power multi-level switching capability together with the low on-current density suggests the application in circuits for massive parallel computation. In this work, we discuss one example circuit of a differential synaptic cell featuring multiple parallel connected FTJ devices. Moreover, from the circuit requirements we deduce that the absolute difference in currents (Ion - Ioff) is a more critical figure of merit than the tunneling electroresistance ratio (TER). Based on this, we discuss the potential of FTJ device optimization by means of electrode work function engineering in bilayer HZO/Al2O3 FTJs.

physics.app-ph

Optimizing nucleation layers for the integration of ferroelectric HZO on CVD-grown graphene

Direct integration of ferroelectric Hf0.5Zr0.5O2 (HZO) on the inert surface of graphene is challenging. Here, using nucleation layers to promote atomic layer deposition of HZO was investigated. Different metals were deposited as nucleation layers via dc sputtering. Ta, which oxidizes in air to form a sub-stoichiometric oxide, was compared to Pt, which offers a more stable electrode. For thicker interlayers, Ta leads to unstable switching behavior of the HZO film. Conversely, at smaller thicknesses, a higher Pr can be achieved with an oxidized Ta interlayer. In both cases, Pt offers higher endurance. The choice of interlayer may strongly depend on the required application.

cond-mat.mtrl-sci

Investigating charge trapping in ferroelectric thin films through transient measurements

A measurement technique is presented to quantify the polarization loss in ferroelectric thin films as a function of delay time during the first 100s after switching. This technique can be used to investigate charge trapping in ferroelectric thin films by analyzing the magnitude and rate of polarization loss. Exemplary measurements have been performed on Hf0.5Zr0.5O2 (HZO) and HZO/Al2O3 films, as a function of pulse width and temperature. It is found that the competing effects of the depolarization field, internal bias field and charge trapping lead to a characteristic Gaussian dependence of the rate of polarization loss on the delay time. From this, a charge trapping and screening model could be identified which describes the dynamics of polarization loss on short timescales.

cond-mat.mtrl-sci

C-AND: Mixed Writing Scheme for Disturb Reduction in 1T Ferroelectric FET Memory

Ferroelectric field effect transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low-power, and non-volatile memories. In this paper, we propose a memory architecture named crossed-AND (C-AND), in which each storage cell consists of a single ferroelectric transistor. The write operation is performed using different write schemes and different absolute voltages, to account for the asymmetric switching voltages of the FeFET. It enables writing an entire wordline in two consecutive cycles and prevents current and power through the channel of the transistor. During the read operation, the current and power are mostly sensed at a single selected device in each column. The read scheme additionally enables reading an entire word without read errors, even along long bitlines. Our Simulations demonstrate that, in comparison to the previously proposed AND architecture, the C-AND architecture diminishes read errors, reduces write disturbs, enables the usage of longer bitlines, and saves up to 2.92X in memory cell area.

eess.SY

A 120dB Programmable-Range On-Chip Pulse Generator for Characterizing Ferroelectric Devices

Novel non-volatile memory devices based on ferroelectric thin films represent a promising emerging technology that is ideally suited for neuromorphic applications. The physical switching mechanism in such films is the nucleation and growth of ferroelectric domains. Since this has a strong dependence on both pulse width and voltage amplitude, it is important to use precise pulsing schemes for a thorough characterization of their behaviour. In this work, we present an on-chip 120 dB programmable range pulse generator, that can generate pulse widths ranging from 10ns to 10ms $\pm$2.5% which eliminates the RLC bottleneck in the device characterisation setup. We describe the pulse generator design and show how the pulse width can be tuned with high accuracy, using Digital to Analog converters. Finally, we present experimental results measured from the circuit, fabricated using a standard 180nm CMOS technology.

cs.ET

2022 Roadmap on Neuromorphic Computing and Engineering

Modern computation based on the von Neumann architecture is today a mature cutting-edge science. In the Von Neumann architecture, processing and memory units are implemented as separate blocks interchanging data intensively and continuously. This data transfer is responsible for a large part of the power consumption. The next generation computer technology is expected to solve problems at the exascale with 1018 calculations each second. Even though these future computers will be incredibly powerful, if they are based on von Neumann type architectures, they will consume between 20 and 30 megawatts of power and will not have intrinsic physically built-in capabilities to learn or deal with complex data as our brain does. These needs can be addressed by neuromorphic computing systems which are inspired by the biological concepts of the human brain. This new generation of computers has the potential to be used for the storage and processing of large amounts of digital information with much lower power consumption than conventional processors. Among their potential future applications, an important niche is moving the control from data centers to edge devices. The aim of this Roadmap is to present a snapshot of the present state of neuromorphic technology and provide an opinion on the challenges and opportunities that the future holds in the major areas of neuromorphic technology, namely materials, devices, neuromorphic circuits, neuromorphic algorithms, applications, and ethics. The Roadmap is a collection of perspectives where leading researchers in the neuromorphic community provide their own view about the current state and the future challenges. We hope that this Roadmap will be a useful resource to readers outside this field, for those who are just entering the field, and for those who are well established in the neuromorphic community. https://doi.org/10.1088/2634-4386/ac4a83

cs.ET

Ferroelectric Tunneling Junctions for Edge Computing

Ferroelectric tunneling junctions (FTJ) are considered to be the intrinsically most energy efficient memristors. In this work, specific electrical features of ferroelectric hafnium-zirconium oxide based FTJ devices are investigated. Moreover, the impact on the design of FTJ-based circuits for edge computing applications is discussed by means of two example circuits.

cs.ET

Hafnia-based Double Layer Ferroelectric Tunnel Junctions as Artificial Synapses for Neuromorphic Computing

Ferroelectric tunnel junctions (FTJ) based on hafnium zirconium oxide (Hf1-xZrxO2; HZO) are a promising candidate for future applications, such as low-power memories and neuromorphic computing. The tunneling electroresistance (TER) is tunable through the polarization state of the HZO film. To circumvent the challenge of fabricating thin ferroelectric HZO layers in the tunneling range of 1-3 nm range, ferroelectric/dielectric double layer sandwiched between two symmetric metal electrodes are used. Due to the decoupling of the ferroelectric polarization storage layer and a dielectric tunneling layer with a higher bandgap, a significant TER ratio between the two polarization states is obtained. By exploiting previously reported switching behaviour and the gradual tunability of the resistance, FTJs can be used as potential candidates for the emulation of synapses for neuromorphic computing in spiking neural networks. The implementation of two major components of a synapse are shown: long term depression/potentiation by varying the amplitude/width/number of voltage pulses applied to the artificial FTJ synapse, and spike-timing-dependent-plasticity curves by applying time-delayed voltages at each electrode. These experimental findings show the potential of spiking neural networks and neuromorphic computing that can be implemented with hafnia-based FTJs.

physics.app-ph

Antiferroelectric negative capacitance from a structural phase transition in zirconia

Crystalline materials with broken inversion symmetry can exhibit a spontaneous electric polarization, which originates from a microscopic electric dipole moment. Long-range polar or anti-polar order of such permanent dipoles gives rise to ferroelectricity or antiferroelectricity, respectively. However, the recently discovered antiferroelectrics of fluorite structure (HfO$_2$ and ZrO$_2$) are different: A non-polar phase transforms into a polar phase by spontaneous inversion symmetry breaking upon the application of an electric field. Here, we show that this structural transition in antiferroelectric ZrO$_2$ gives rise to a negative capacitance, which is promising for overcoming the fundamental limits of energy efficiency in electronics. Our findings provide insight into the thermodynamically 'forbidden' region of the antiferroelectric transition in ZrO$_2$ and extend the concept of negative capacitance beyond ferroelectricity. This shows that negative capacitance is a more general phenomenon than previously thought and can be expected in a much broader range of materials exhibiting structural phase transitions.

cond-mat.mtrl-sci

Ferroelectric Negative Capacitance Domain Dynamics

Transient negative capacitance effects in epitaxial ferroelectric Pb(Zr$_{0.2}$Ti$_{0.8}$)O$_3$ capacitors are investigated with a focus on the dynamical switching behavior governed by domain nucleation and growth. Voltage pulses are applied to a series connection of the ferroelectric capacitor and a resistor to directly measure the ferroelectric negative capacitance during switching. A time-dependent Ginzburg-Landau approach is used to investigate the underlying domain dynamics. The transient negative capacitance is shown to originate from reverse domain nucleation and unrestricted domain growth. However, with the onset of domain coalescence, the capacitance becomes positive again. The persistence of the negative capacitance state is therefore limited by the speed of domain wall motion. By changing the applied electric field, capacitor area or external resistance, this domain wall velocity can be varied predictably over several orders of magnitude. Additionally, detailed insights into the intrinsic material properties of the ferroelectric are obtainable through these measurements. A new method for reliable extraction of the average negative capacitance of the ferroelectric is presented. Furthermore, a simple analytical model is developed, which accurately describes the negative capacitance transient time as a function of the material properties and the experimental boundary conditions.

cond-mat.mes-hall

A computational study of hafnia-based ferroelectric memories: from ab initio via physical modeling to circuit models of ferroelectric device

The discovery of ferroelectric properties of binary oxides revitalized the interest in ferroelectrics and bridged the scaling gap between the state-of-the-art semiconductor technology and ferroelectric memories. However, before hitting the markets, the origin of ferroelectricity and in-depth studies of device characteristics are needed. Establishing a correlation between the performance of the device and underlying physical mechanisms is the first step toward understanding the device and engineering guidelines for a novel, superior device. Therefore, in this paper a holistic modeling approaches which lead to a better understanding of ferroelectric memories based on hafnium and zirconium oxide is addressed. Starting from describing the stabilization of the ferroelectric phase within the binary oxides via physical modeling the physical mechanisms of the ferroelectric devices are reviewed. Besides, limitations and modeling of the multilevel operation and switching kinetics of ultimately scaled devices as well as the necessity for Landau-Khalatnikov approach are discussed. Furthermore, a device-level model of ferroelectric memory devices that can be used to study the array implementation and their operational schemes are addressed. Finally, a circuit model of the ferroelectric memory device is presented and potential further applications of ferroelectric devices are outlined.

cond-mat.mtrl-sci

Substrate effect on the resistive switching in BiFeO3 thin films

BiFeO3 thin films have been deposited on Pt/sapphire and Pt/Ti/SiO2/Si substrates with pulsed laser deposition using the same growth conditions, respectively. Au was sputtered as the top electrode. The microscopic structure of the thin film varies by changing the underlying substrate. Thin films on Pt/sapphire are not resistively switchable due to the formation of Schottky contacts at both the top and the bottom interface. However, thin films on Pt/Ti/SiO2/Si exhibit an obvious resistive switching behavior under forward bias. The conduction mechanisms in BiFeO3 thin films on Pt/sapphire and Pt/Ti/SiO2/Si substrates are discussed to understand the different resistive switching behaviors.

cond-mat.mtrl-sci