arXiv subjects
Publications and source records attributed to Vincent Bayot.
Process simulation are performed in order to simulate the full fabrication process of an alternative nano-flash memory in order to optimise it and to improve the understanding of the dot storage formation. The influence of various parameters (oxidation temperature, nanowire shape) have been investigated.
The Braess paradox, known for traffic and other classical networks, lies in the fact that adding a new route to a congested network in an attempt to relieve congestion can counter-intuitively degrade the overall network performance. Recently, we have extended the concept of Braess paradox to semiconductor mesoscopic networks, whose transport properties are governed by quantum physics. In this paper, we demonstrate theoretically that, alike in classical systems, congestion plays a key role in the occurrence of a Braess paradox in mesoscopic networks.
Self-aligned single-dot memory devices and arrays were fabricated based on arsenic-assisted etching and oxidation effects. The resulting device has a floating gate of about 5-10 nm, presenting single-electron memory operation at room temperature. In order to realize the final single-electron memory circuit, this paper investigates process repeatability, device uniformity in single-dot memory arrays, device scalability, and process transferability to an industrial application.
This paper presents the process optimization of a single-electron nanoflash electron memory. Self-aligned single dot memory structures have been fabricated using a wet anisotropic oxidation of a silicon nanowire. One of the main issue was to clarify the process conditions for the dot formation. Based on the process modeling, the influence of various parameters (oxidation temperature, nanowire shape) has been investigated. The necessity of a sharp compromise between these different parameters to ensure the presence of the memory dot has been established. In order to propose an aggressive memory cell, the downscaling of the device has been carefully studied. Scaling rules show that the size of the original device could be reduced by a factor of 2. This point has been previously confirmed by the realization of single-electron memory devices.
This paper presents a brief review of scanning-gate microscopy applied to the imaging of electron transport in buried semiconductor quantum structures. After an introduction to the technique and to some of its practical issues, we summarise a selection of its successful achievements found in the literature, including our own research. The latter focuses on the imaging of GaInAs-based quantum rings both in the low magnetic field Aharonov-Bohm regime and in the high-field quantum Hall regime. Based on our own experience, we then discuss in detail some of the limitations of scanning-gate microscopy. These include possible tip induced artefacts, effects of a large bias applied to the scanning tip, as well as consequences of unwanted charge traps on the conductance maps. We emphasize how special care must be paid in interpreting these scanning-gate images.