arXiv subjects

Younes Otarid

Publications and source records attributed to Younes Otarid.

10 recordsLinked to original sources

arXiv2026

Design and performance of the Fast Beam Condition Monitor for luminosity and background measurement at the CMS Experiment in LHC Run 3

The Fast Beam Condition Monitor (BCM1F) has been used at the CMS Experiment since the first LHC circulating beams in 2008. Originally meant as a beam-induced background monitor for fast beam losses detection, it showed a potential also for luminosity measurements in 2012 running, and has been used for luminosity measurements since the beginning of Run 2 data taking in 2015 as a part of the Beam Radiation, Instrumentation and Luminosity (BRIL) system. Over the years, the system has undergone various upgrades to the sensors, the front-end and back-end electronics, providing improvements in the precision of the measurements, that remain valid in the higher pileup conditions of LHC Run 3 (2022-2026). Based on the experience of all BCM1F Run 2 upgrades, the detector was completely rebuilt prior to LHC Run 3 using AC-coupled silicon-pad diodes and active cooling. This latest detector version exhibits excellent linearity with instantaneous luminosity and achieves nanosecond-level timing precision, enabling improved systematic corrections for luminosity and background measurements. This paper presents a detailed overview of the detector system for LHC Run 3, including the selection and qualification of sensors as well as a summary of the readout system. It also outlines the processing and calibration strategy for luminosity data, discussing operational hurdles and comparing BCM1F measurements to other CMS luminosity measurements to assess the system's performance as a luminometer. Lastly, the implications for the design of a future luminosity detector to be used in the envisioned HL-LHC upgrade are discussed.

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arXiv2026

Advancements and future expansions of the Caribou DAQ system

Caribou is a versatile data acquisition (DAQ) system developed within several collaborative frameworks (CERN EP R&D, DRD3, AIDAinnova, and Tangerine) to support laboratory and test-beam characterization of novel silicon pixel detectors. It combines a custom Control and Readout (CaR) board with a Xilinx Zynq System-on-Chip (SoC) running project-wide shared firmware and software stacks. The system architecture emphasizes reusability, flexibility, and ease of integration. The CaR board provides essential interfaces such as programmable power supplies, voltage and current references, high-speed ADCs, and configurable I/O lines for detector control and readout. The SoC runs an embedded Linux distribution built with PetaLinux and integrates two main components: Peary, a C++ embedded DAQ application providing hardware abstraction, configuration management, logging, and multi-device control through Command Line (CLI) and Python interfaces; and Boreal, a common Caribou FPGA firmware framework offering reusable modules and automated build workflows for user-specific bit files. The next major milestone in Caribou's evolution is the transition to version 2.0, based on a Zynq UltraScale+ System-on-Module (SoM) architecture. This paper presents the recent progress and future prospects of the project and describes recent hardware, firmware, and software developments preparing the system for the upcoming CaR board v2.0.

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arXiv2026

Characterization of the H2M Monolithic CMOS Sensor

The H2M (Hybrid-to-Monolithic) is a monolithic pixel sensor manufactured in a modified \SI{65}{\nano\meter}~CMOS imaging process with a small collection electrode. Its design addresses the challenges of porting an existing hybrid pixel detector architecture into a monolithic chip, using a digital-on-top design methodology, and developing a compact digital cell library. Each square pixel integrates an analog front-end and digital pulse processing with an 8-bit counter within a \SI{35}{\micro\meter}~pitch. This contribution presents the performance of H2M based on laboratory and test beam measurements, including a comparison with analog front-end simulations in terms of gain and noise. A particular emphasis is placed on backside thinning in order to reduce material budget, down to a total chip thickness of \SI{21}{\micro\meter} for which no degradation in MIP detection performance is observed. For all investigated samples, a MIP detection efficiency above \SI{99}{\%} is achieved below a threshold of approximately 205 electrons. At this threshold, the fake-hit rate corresponds to a matrix occupancy of fewer than one pixel per the \SI{500}{\nano\second}~frame. Measurements reveal a non-uniform in-pixel response, attributed to the formation of local potential wells in regions with low electric field. A simulation flow combining technology computer-aided design, Monte Carlo, and circuit simulations is used to investigate and describe this behavior, and is applied to develop mitigation strategies for future chip submissions with similar features.

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arXiv2025

Caribou - A versatile data acquisition system for silicon pixel detector prototyping

Caribou is a versatile data acquisition system used in multiple collaborative frameworks (CERN EP R&D, DRD3, AIDAinnova, Tangerine) for laboratory and test-beam qualification of novel silicon pixel detector prototypes. The system is built around a common hardware, firmware and software stack shared accross different projects, thereby drastically reducing the development effort and cost. It consists of a custom Control and Readout (CaR) board and a commercial Xilinx Zynq System-on-Chip (SoC) platform. The SoC platform runs a full Yocto distribution integrating the custom software framework (Peary) and a custom FPGA firmware built within a common firmware infrastructure (Boreal). The CaR board provides a hardware environment featuring various services such as powering, slow-control, and high-speed data links for the target detector prototype. Boreal and Peary, in turn, offer firmware and software architectures that enable seamless integration of control and readout for new devices. While the first version of the system used a SoC platform based on the ZC706 evaluation board, migration to a Zynq UltraScale+ architecture is progressing towards the support of the ZCU102 board and the ultimate objective of integrating the SoC functionality directly into the CaR board, eliminating the need for separate evaluation boards. This paper describes the Caribou system, focusing on the latest project developments and showcasing progress and future plans across its hardware, firmware, and software components.

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arXiv2025

Yield, noise and timing studies of ALICE ITS3 stitched sensor test structures: the MOST

In the LHC long shutdown 3, the ALICE experiment upgrades the inner layers of its Inner Tracker System with three layers of wafer-scale stitched sensors bent around the beam pipe. Two stitched sensor evaluation structures, the MOnolithic Stitched Sensor (MOSS) and MOnolithic Stitched Sensor with Timing (MOST) allow the study of yield dependence on circuit density, power supply segmentation, stitching demonstration for power and data transmission, performance dependence on reverse bias, charge collection performance, parameter uniformity across the chip, and performance of wafer-scale data transmission. The MOST measures 25.9 cm x 0.25 cm, has more than 900,000 pixels of 18x18 $μ$m$^2$ and emphasizes the validation of pixel circuitry with maximum density, together with a high number of power domains separated by switches allowing to disconnect faulty circuits. It employs 1 Gb/s 26 cm long data transmission using asynchronous, data-driven readout. This readout preserves information on pixel address, time of arrival and time over threshold. In the MOSS, by contrast, regions with different in-pixel densities are implemented to study yield dependence and are read synchronously. MOST test results validated the concept of power domain switching and the data transmission over 26 cm stitched lines which are to be employed on the full-size, full-functionality ITS3 prototype sensor, MOSAIX. Jitter of this transmission is still under study. This proceeding summarizes the performance of the stitched sensor test structures with emphasis on the MOST.

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arXiv2025

The H2M Monolithic Active Pixel Sensor -- characterizing non-uniform in-pixel response in a 65 nm CMOS imaging technology

The high energy physics community recently gained access to the TPSCo 65 nm ISC (Image Sensor CMOS), which enables a higher in-pixel logic density in monolithic active pixel sensors (MAPS) compared to processes with larger feature sizes. To explore this novel technology, the Hybrid-to-Monolithic (H2M) test chip has been designed and manufactured. The design followed a digital-on-top design workflow and ports a hybrid pixel-detector architecture, with digital pulse processing in each pixel, into a monolithic chip. The chip matrix consists of 64$\times$16 square pixels with a size of 35$\times$35 um2, and a total active area of approximately 1.25 um2. The chip has been successfully integrated into the Caribou DAQ system. It is fully functional, and the measured threshold dispersion and noise agree with the expectation from front-end simulations. However, a non-uniform in-pixel response related to the size and location of the n-wells in the analog circuitry has been observed in test beam measurements and will be discussed in this contribution. This asymmetry in the pixel response, enhanced by the 35 um pixel pitch - larger than in other prototypes - and certain features of the readout circuit, has not been observed in prototypes with smaller pixel pitches in this technology.

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arXiv2025

Impact of the circuit layout on the charge collection in a monolithic pixel sensor

CERN's strategic R&D programme on technologies for future experiments recently started investigating the TPSCo 65nm ISC CMOS imaging process for monolithic active pixels sensors for application in high energy physics. In collaboration with the ALICE experiment and other institutes, several prototypes demonstrated excellent performance, qualifying the technology. The Hybrid-to-Monolithic (H2M), a new test-chip produced in the same process but with a larger pixel pitch than previous prototypes, exhibits an unexpected asymmetric efficiency pattern. This contribution describes a simulation procedure combining TCAD, Monte Carlo and circuit simulations to model and understand this effect. It proved able to reproduce measurement results and attribute the asymmetric efficiency drop to a slow charge collection due to low amplitude potential wells created by the circuitry layout and impacting efficiency via ballistic deficit.

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arXiv2025

Laboratory and beam-test performance study of a 55$~μ$m pitch iLGAD sensor bonded to a Timepix3 readout chip

This contribution reports on characterisation results of a large-area (2$~\mathrm{cm}^2$) small pitch (55$~μ$m) inverse Low-Gain Avalanche Detector (iLGAD), bonded to a Timepix3 readout chip. The ilGAD sensors were produced by Micron Semiconductor Ltd with the goal to obtain good gain uniformity and maximise the fill-factor -- an issue present with standard small-pitch LGAD designs. We have conducted detailed performance evaluations using both X-ray calibrations and beam tests. An X-ray fluorescence setup has been used to obtain energy calibration and to identify the optimal operating settings of the new devices, whereas the extensive beam tests allowed for a detailed evaluation of the detector performance. The beam-tests were performed at the CERN SPS North Area H6 beamline, using a 120 GeV/c pion beam. The reference tracking and time-stamping is achieved by a Timepix3-based beam telescope setup. The results show a gain of around 5 with very good uniformity, measured across the whole gain area, as well as a hit time resolution down to 1.3 ns without correcting for the time-walk effects. Furthermore, it is shown that the gain opens the possibility of a good X-ray energy resolution down to 4.5 keV.

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arXiv2022

The ECFA Early Career Researcher's Panel: composition, structure, and activities, 2021 -- 2022

The European Committee for Future Accelerators (ECFA) Early Career Researcher's (ECR) panel, which represents the interests of the ECR community to ECFA, officially began its activities in January 2021. In the first two years, the panel has defined its own internal structure, responded to ECFA requests for feedback, and launched its own initiatives to better understand and support the diverse interests of early career researchers. This report summarises the panel composition and structure, as well as the different activities the panel has been involved with during the first two years of its existence.

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arXiv2021

Results of the 2021 ECFA Early-Career Researcher Survey on Training in Instrumentation

The European Committee for Future Accelerators (ECFA) Early-Career Researchers (ECR) Panel was invited by the ECFA Detector R&D Roadmap conveners to collect feedback from the European ECR community. A working group within the ECFA ECR panel held a Townhall Meeting to get first input, and then designed and broadly circulated a detailed survey to gather feedback from the larger ECR community. A total of 473 responses to this survey were received, providing a useful overview of the experiences of ECRs in instrumentation training and related topics. This report summarises the feedback received, and is intended to serve as an input to the ECFA Detector R&D Roadmap process.

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