arXiv · 2503.21853
Impact of the circuit layout on the charge collection in a monolithic pixel sensor
Abstract
CERN's strategic R&D programme on technologies for future experiments recently started investigating the TPSCo 65nm ISC CMOS imaging process for monolithic active pixels sensors for application in high energy physics. In collaboration with the ALICE experiment and other institutes, several prototypes demonstrated excellent performance, qualifying the technology. The Hybrid-to-Monolithic (H2M), a new test-chip produced in the same process but with a larger pixel pitch than previous prototypes, exhibits an unexpected asymmetric efficiency pattern. This contribution describes a simulation procedure combining TCAD, Monte Carlo and circuit simulations to model and understand this effect. It proved able to reproduce measurement results and attribute the asymmetric efficiency drop to a slow charge collection due to low amplitude potential wells created by the circuitry layout and impacting efficiency via ballistic deficit.
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Corentin Lemoine, Rafael Ballabriga, Eric Buschmann, Michael Campbell, Raimon Casanova Mohr, Dominik Dannheim, Jona Dilg, Ana Dorda, Finn King, Ono Feyens, Philipp Gadow, Ingrid-Maria Gregor, Karsten Hansen, Yajun He, Lennart Huth, Iraklis Kremastiotis, Stefano Maffessanti, Larissa Mendes, Younes Otarid, Christian Reckleben, Sébastien Rettie, Manuel Alejandro del Rio Viera, Sara Ruiz Daza, Judith Schlaadt, Adriana Simancas, Walter Snoeys, Simon Spannagel, Tomas Vanat, Anastasiia Velyka, Gianpiero Vignola, Håkan Wennlöf. 2025-03-27. Impact of the circuit layout on the charge collection in a monolithic pixel sensor. https://arxiv.org/abs/2503.21853
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