Hardware Demonstrator of a Compact First-Level Muon Track Trigger for Future Hadron Collider Experiments

Abstract

Single muon triggers are crucial for the physics programmes at hadron collider experiments. To be sensitive to electroweak processes, single muon triggers with transverse momentum thresholds down to 20 GeV and dimuon triggers with even lower thresholds are required. In order to keep the rates of these triggers at an acceptable level these triggers have to be highly selective, i.e. they must have small accidental trigger rates and sharp trigger turn-on curves. The muon systems of the LHC experiments and experiments at future colliders like FCC-hh will use two muon chamber systems for the muon trigger, fast trigger chambers like RPCs with coarse spatial resolution and much slower precision chambers like drift-tube chambers with high spatial resolution. The data of the trigger chambers are used to identify the bunch crossing in which the muon was created and for a rough momentum measurement while the precise measurements of the muon trajectory by the precision chambers are ideal for an accurate muon momentum measurement. A compact muon track finding algorithm is presented, where muon track candidates are reconstructed using a binning algorithm based on a 1D Hough Transform. The algorithm has been designed and implemented on a System-On-Chip device. A hardware demonstration using Xilinx Evaluation boards ZC706 has been set-up to prove the concept. The system has demonstrated the feasibility to reconstruct muon tracks with a good angular resolution, whilst satisfying latency constraints. The demonstrated track-reconstruction system, the chosen architecture, the achievements to date and future options for such a system will be discussed.