Laser Processing For 3D Junctionless Transistor Fabrication

D. Bosch; P. Acosta Alba; S. Kerdiles; V. Benevent; C. Perrot; J. Lassarre; J. Richy; J. Lacord; B. Sklenard; L. Brunet; P. Batude; C. Fenouillet-Beranger; D. Lattard; J. P. Colinge; F. Balestra; F. Andrieu

arXiv · 2011.15061

Laser Processing For 3D Junctionless Transistor Fabrication

D. Bosch·P. Acosta Alba·S. Kerdiles·V. Benevent·C. Perrot·J. Lassarre·J. Richy·J. Lacord·B. Sklenard·L. Brunet·P. Batude·C. Fenouillet-Beranger·D. Lattard·J. P. Colinge·F. Balestra·F. Andrieu

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Abstract

To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-silicon film featuring excellent roughness values (Rmax= 1.6nm and RMS=0.2nm). Guidelines for grain size optimization using nanosecond (ns) laser annealing are given.

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D. Bosch, P. Acosta Alba, S. Kerdiles, V. Benevent, C. Perrot, J. Lassarre, J. Richy, J. Lacord, B. Sklenard, L. Brunet, P. Batude, C. Fenouillet-Beranger, D. Lattard, J. P. Colinge, F. Balestra, F. Andrieu. 2020-11-30. Laser Processing For 3D Junctionless Transistor Fabrication. https://arxiv.org/abs/2011.15061

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