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arXiv · 2208.12498

A low dead time, resource efficient encoding method for FPGA based high-resolution TDL TDCs

Wenhao Dong·Changqing Feng·Junchen Wang·Zhongtao Shen·Shubin Liu·Qi An
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Abstract

This paper presents a novel encoding method for fine time data of a tapped delay line (TDL) time-to-digital Converter (TDC). It is based on divide-and-conquer strategy, and has the advantage of significantly reducing logic resource utilization while retaining low dead-time performance. Furthermore, the problem of high bubble depth in advanced devices can be resolved with this method. Four examples are demonstrated, which were implemented in a Xilinx Artix-7 Field Programmable Gate Array (FPGA) device, and encoding method presented in this paper was employed to encode fine time data for normal TDL TDC, a half-length delay line TDC, and double-edge and four-edge wave union TDCs. Compared with TDCs from the latest published papers that adopt traditional encoders, the logic utilization of TDCs in this paper were reduced by a factor of 45% to 70% in different situations, while the encoding dead time can be restricted in one clock cycle. Acceptable resolutions of the demonstrated TDCs were also obtained, proving the functionality of the encoding method.

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Wenhao Dong, Changqing Feng, Junchen Wang, Zhongtao Shen, Shubin Liu, Qi An. 2022-08-26. A low dead time, resource efficient encoding method for FPGA based high-resolution TDL TDCs. https://arxiv.org/abs/2208.12498

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