Hysteresis Measurements as a Diagnostic Tool: A Systematic Approach for Stability Benchmarking and Performance Projection of 2D-Materials-Based MOSFETs

Abstract

Judging by its omnipresence in the literature, the hysteresis observed in the transfer characteristics of emerging transistors based on 2D-materials is widely accepted as an important metric related to the device quality. The hysteresis is often reported with attributes like "negligible" or "small" without giving any specifics as to how this was determined and against what reference the measured values were compared to. Quite surprisingly, there appears to be only a fragmentary understanding of the mechanisms actually contributing to hysteresis and the sensitivity of the actual measurement on various experimental parameters. We attempt to close this gap by first providing a comprehensive theoretical analysis of the dominant mechanisms contributing to hysteresis: charge trapping by defects from the channel or the gate, the drift of mobile charges, and eventually ferroelectricity. We continue by suggesting methods to experimentally distinguishing between these phenomena. Based on these discussions it becomes clear that previously reported hysteresis values have little meaning as they have been non-systematically recorded under arbitrary conditions. In order to resolve this predicament, we propose a standardized hysteresis measurement scheme to establish the hysteresis as a comparable metric for the assessment of device stability. Our standardized scheme ensures that hysteresis data can be effectively compared across different technologies and, most importantly, provide a means to extrapolate data obtained on thicker prototypes to subnanometer equivalent oxide thicknesses. This facilitates the systematic benchmarking of insulator/channel combinations in terms of stability, which thereby enables the screening of material systems for more stable and reliable 2D-material-based MOSFETs.