arXiv · 2510.15275
Unveiling Retention Loss Mechanism in FeFETs with Gate-side Interlayer by Decoupling Trapped Charges and Ferroelectric Polarization
Abstract
We propose a direct experimental extraction technique for trapped charges and quantitative energy band diagrams in the FeFETs with metal-insulator-ferroelectric-insulator-semiconductor (MIFIS) structure, derived from the physical relationship between Vth and gate-side interlayer (G.IL) thickness. By decoupling trapped charges and ferroelectric polarization, we reveal that: (i) The gateinjected charges and channel-injected charges are excessive and maintain consistent ratios to ferroelectric polarization (~170% and ~130%, respectively). (ii) Retention loss originates from the detrapping of gate-injected charges rather than ferroelectric depolarization. (iii) As the G.IL thickens, the gate-injected charge de-trapping path transforms from gate-side to channel-side. To address the retention loss, careful material design, optimization, and bandgap engineering in the MIFIS structure are crucial. This work advances the understanding of high retention strategies for MIFIS-FeFETs in 3D FE NAND.
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Runhao Han, Tao Hu, Jia Yang, Saifei Dai, Yajing Ding, Mingkai Bai, Xianzhou Shao, Junshuai Chai, Hao Xu, Qing Luo, Wenwu Wang, Tianchun Ye, Xiaolei Wang. 2025-10-17. Unveiling Retention Loss Mechanism in FeFETs with Gate-side Interlayer by Decoupling Trapped Charges and Ferroelectric Polarization. https://arxiv.org/abs/2510.15275
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