arXiv subjects

Tianchun Ye

Publications and source records attributed to Tianchun Ye.

10 recordsLinked to original sources

arXiv2026

DSPE: An Energy-Efficient Edge Processor for DeepSeek Inference with MerkleTree-based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing

In recent years, DeepSeek has achieved strong inference performance but remains hard to deploy on energy-constrained edge devices. This paper presents the DeepSeek Processing Element (DSPE), an edge-oriented architecture that alleviates the model's heavy computational and energy demands. DSPE introduces three techniques: the MerkleTree-based Incremental Pruning Scheme (MIPS) for secure redundant-vector reduction, the Multi-Stage Boothing Lookup Method (MBLM) for bit-flip-aware approximate multiplication, and the Dynamic Adaptive Posit Processing Mechanism (DAPPM), which introduces a new DA-Posit format and its corresponding hardware multiplication architecture. Implemented in TSMC 28nm CMOS, DSPE achieves 109.4 TFLOPS/W energy efficiency compared with state-of-the-art designs and offers a scalable foundation for edge deployment.

cs.AR↗

arXiv2025

Investigation of the Physical Mechanism behind Retention Loss in FeFETs with MIFIFIS Gate Structure

A Metal-Gate Blocking Layer (GBL)- Ferroelectric-Tunnel Dielectric Layer (TDL)-Ferroelectric -Channel Insulator (Ch.IL)-Si (MIFIFIS) structure is proposed to achieve a larger MW for applications in Fe-NAND. However, the large retention loss (RL) in the MIFIFIS structure restricts its application. In this work, we vary the physical thickness of the GBL and TDL, and conduct an in-depth analysis of the energy bands of the gate structure to investigate the physical mechanism behind the RL in FeFETs with the MIFIFIS structure. The physical origin of the RL is that the electric field direction across the TDL reduces the potential barrier provided by the ferroelectric near the silicon substrate. Based on the above physical mechanism, the RL can be reduced to 12% and 0.2% by redesigning the gate structure or reducing the pulse amplitude, respectively. Our work contributes to a deeper understanding of the physical mechanism behind the RL in FeFETs with the MIFIFIS gate structure. It provides guidance for enhancing the reliability of FeFETs.

physics.app-ph↗

arXiv2025

Unveiling Retention Loss Mechanism in FeFETs with Gate-side Interlayer by Decoupling Trapped Charges and Ferroelectric Polarization

We propose a direct experimental extraction technique for trapped charges and quantitative energy band diagrams in the FeFETs with metal-insulator-ferroelectric-insulator-semiconductor (MIFIS) structure, derived from the physical relationship between Vth and gate-side interlayer (G.IL) thickness. By decoupling trapped charges and ferroelectric polarization, we reveal that: (i) The gateinjected charges and channel-injected charges are excessive and maintain consistent ratios to ferroelectric polarization (~170% and ~130%, respectively). (ii) Retention loss originates from the detrapping of gate-injected charges rather than ferroelectric depolarization. (iii) As the G.IL thickens, the gate-injected charge de-trapping path transforms from gate-side to channel-side. To address the retention loss, careful material design, optimization, and bandgap engineering in the MIFIS structure are crucial. This work advances the understanding of high retention strategies for MIFIS-FeFETs in 3D FE NAND.

physics.app-ph↗

arXiv2024

Effect of Top Al$_2$O$_3$ Interlayer Thickness on Memory Window and Reliability of FeFETs With TiN/Al$_2$O$_3$/Hf$_{0.5}$Zr$_{0.5}$O$_2$/SiO$_x$/Si (MIFIS) Gate Structure

We investigate the effect of top Al2O3 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistors (Si-FeFETs) with TiN/Al$_2$O$_3$/Hf$_{0.5}$Zr$_{0.5}$O$_2$/SiO$_x$/Si (MIFIS) gate structure. We find that the MW first increases and then remains almost constant with the increasing thickness of the top Al2O3. The phenomenon is attributed to the lower electric field of the ferroelectric Hf$_{0.5}$Zr$_{0.5}$O$_2$ in the MIFIS structure with a thicker top Al2O3 after a program operation. The lower electric field makes the charges trapped at the top Al2O3/Hf0.5Zr0.5O$_2$ interface, which are injected from the metal gate, cannot be retained. Furthermore, we study the effect of the top Al$_2$O$_3$ interlayer thickness on the reliability (endurance characteristics and retention characteristics). We find that the MIFIS structure with a thicker top Al$_2$O$_3$ interlayer has poorer retention and endurance characteristics. Our work is helpful in deeply understanding the effect of top interlayer thickness on the MW and reliability of Si-FeFETs with MIFIS gate stacks.

cond-mat.mtrl-sci↗

arXiv2024

High Mobility SiGe/Ge 2DHG Heterostructure Quantum Wells for Semiconductor Hole Spin Qubits

Strong spin-orbit coupling and relatively weak hyperfine interactions make germanium hole spin qubits a promising candidate for semiconductor quantum processors. The two-dimensional hole gas structure of strained Ge quantum wells serves as the primary material platform for spin hole qubits.A low disorder material environment is essential for this process. In this work, we fabricated a Ge/SiGe heterojunction with a 60 nm buried quantum well layer on a Si substrate using reduced pressure chemical vapor deposition technology. At a temperature of 16 mK, when the carrier density is 1.87*10^11/cm2, we obtained a mobility as high as 308.64*10^4cm2/Vs. Concurrently, double quantum dot and planar germanium coupling with microwave cavities were also successfully achieved.This fully demonstrates that this structure can be used for the preparation of higher-performance hole spin qubits.

cond-mat.mes-hall↗

arXiv2024

Impact of the Top SiO2 Interlayer Thickness on Memory Window of Si Channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) Gate Structure

We study the impact of top SiO2 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistor (FeFET) with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. We find that the MW increases with the increasing thickness of the top SiO2 interlayer, and such an increase exhibits a two-stage linear dependence. The physical origin is the presence of the different interfacial charges trapped at the top SiO2/Hf0.5Zr0.5O2 interface. Moreover, we investigate the dependence of endurance characteristics on initial MW. We find that the endurance characteristic degrades with increasing the initial MW. By inserting a 3.4 nm SiO2 dielectric interlayer between the gate metal TiN and the ferroelectric Hf0.5Zr0.5O2, we achieve a MW of 6.3 V and retention over 10 years. Our work is helpful in the device design of FeFET.

cond-mat.mtrl-sci↗

arXiv2024

Impact of Top SiO2 interlayer Thickness on Memory Window of Si Channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) Gate Structure

We study the impact of top SiO2 interlayer thickness on memory window of Si channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. The memory window increases with thicker top SiO2. We realize the memory window of 6.3 V for 3.4 nm top SiO2. Moreover, we find that the endurance characteristic degrades with increasing the initial memory window.

physics.app-ph↗

arXiv2022

First-principles study of oxygen vacancy defects in orthorhombic Hf$_{0.5}$Zr$_{0.5}$O$_2$/SiO$_2$/Si gate stack

The gate defect of the ferroelectric HfO$_2$-based Si field-effect transistor (Si FeFET) plays a dominant role in its reliability issue. The first-principles calculations are an effective method for the atomic-scale understanding of gate defects. However, the first-principles study on the defects of FeFET gate stacks, i.e., metal/orthorhombic-Hf$_{0.5}$Zr$_{0.5}$O$_2$/SiO$_2$/Si structure, has not been reported so far. The key challenge is the construction of metal/orthorhombic-Hf$_{0.5}$Zr$_{0.5}$O$_2$/SiO$_2$/Si gate stack models. Here, we use the Hf$_{0.5}$Zr$_{0.5}$O$_2$(130) high-index crystal face as the orthorhombic ferroelectric layer and construct a robust atomic structure of the orthorhombic-Hf$_{0.5}$Zr$_{0.5}$O$_2$/SiO$_2$/Si gate stack without any gap states. Its high structural stability is ascribed to the insulated interface. The calculated band offsets show that this gate structure is of the type-I band alignment. Furthermore, the formation energies and charge transition levels (CTLs) of defects reveal that the oxygen vacancy defects are more favorable to form compared with other defects such as oxygen interstitial and Hf/Zr vacancy, and their CTLs are mainly localized near the Si conduction band minimum and valence band maximum, in agreement with the reported experimental results. The oxygen vacancy defects are responsible for charge trapping/de-trapping behavior in Si FeFET. This work provides an insight into gate defects and paves the way to carry out the first-principles study of ferroelectric HfO$_2$-based Si FeFET.

cond-mat.mtrl-sci↗

arXiv2021

Impact of Interlayer and Ferroelectric Materials on Charge Trapping during Endurance Fatigue of FeFET with TiN/HfxZr1-xO2/interlayer/Si (MFIS) Gate Structure

We study the impact of different interlayers and ferroelectric materials on charge trapping during the endurance fatigue of Si FeFET with TiN/HfxZr1-xO2/interlayer/Si (MFIS) gate stack. We have fabricated FeFET devices with different interlayers (SiO2 or SiON) and HfxZr1-xO2 materials (x=0.75, 0.6, 0.5), and directly extracted the charge trapping during endurance fatigue. We find that: 1) The introduction of the N element in the interlayer suppresses charge trapping and defect generation, and improves the endurance characteristics. 2) As the spontaneous polarization (Ps) of the HfxZr1-xO2 decreases from 25.9 μC/cm2 (Hf0.5Zr0.5O2) to 20.3 μC/cm2 (Hf0.6Zr0.4O2), the charge trapping behavior decreases, resulting in the slow degradation rate of memory window (MW) during program/erase cycling; in addition, when the Ps further decreases to 8.1 μC/cm2 (Hf0.75Zr0.25O2), the initial MW nearly disappears (only ~0.02 V). Thus, the reduction of Ps could improve endurance characteristics. On the contract, it can also reduce the MW. Our work helps design the MFIS gate stack to improve endurance characteristics.

physics.app-ph↗

arXiv2021

Experimental Extraction and Simulation of Charge Trapping during Endurance of FeFET with TiN/HfZrO/SiO2/Si (MFIS) Gate Structure

We investigate the charge trapping during endurance fatigue of FeFET with TiN/Hf0.5Zr0.5O2/SiO2/Si (MFIS) gate structure. We propose a method of experimentally extracting the number of trapped charges during the memory operation, by measuring the charges in the metal gate and Si substrate. We verify that the amount of trapped charges increases during the endurance fatigue process. This is the first time that the trapped charges are directly experimentally extracted and verified to increase during endurance fatigue. Moreover, we model the interplay between the trapped charges and ferroelectric polarization switching during endurance fatigue. Through the consistency of experimental results and simulated data, we demonstrate that as the memory window decreases: 1) The ferroelectric characteristic of Hf0.5Zr0.5O2 is not degraded. 2) The trap density in the upper bandgap of the gate stacks increases. 3) The reason for memory window decrease is increased trapped electrons after program operation but not related to hole trapping/de-trapping. Our work is helpful to study the charge trapping behavior of FeFET and the related endurance fatigue process.

physics.app-ph↗