arXiv subjects

Eric Buschmann

Publications and source records attributed to Eric Buschmann.

17 recordsLinked to original sources

arXiv2025

Advancements and future expansions of the Caribou DAQ system

Caribou is a versatile data acquisition (DAQ) system developed within several collaborative frameworks (CERN EP R&D, DRD3, AIDAinnova, and Tangerine) to support laboratory and test-beam characterization of novel silicon pixel detectors. It combines a custom Control and Readout (CaR) board with a Xilinx Zynq System-on-Chip (SoC) running project-wide shared firmware and software stacks. The system architecture emphasizes reusability, flexibility, and ease of integration. The CaR board provides essential interfaces such as programmable power supplies, voltage and current references, high-speed ADCs, and configurable I/O lines for detector control and readout. The SoC runs an embedded Linux distribution built with PetaLinux and integrates two main components: Peary, a C++ embedded DAQ application providing hardware abstraction, configuration management, logging, and multi-device control through Command Line (CLI) and Python interfaces; and Boreal, a common Caribou FPGA firmware framework offering reusable modules and automated build workflows for user-specific bit files. The next major milestone in Caribou's evolution is the transition to version 2.0, based on a Zynq UltraScale+ System-on-Module (SoM) architecture. This paper presents the recent progress and future prospects of the project and describes recent hardware, firmware, and software developments preparing the system for the upcoming CaR board v2.0.

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arXiv2025

Characterization of the H2M Monolithic CMOS Sensor

The H2M (Hybrid-to-Monolithic) is a monolithic pixel sensor manufactured in a modified \SI{65}{\nano\meter}~CMOS imaging process with a small collection electrode. Its design addresses the challenges of porting an existing hybrid pixel detector architecture into a monolithic chip, using a digital-on-top design methodology, and developing a compact digital cell library. Each square pixel integrates an analog front-end and digital pulse processing with an 8-bit counter within a \SI{35}{\micro\meter}~pitch. This contribution presents the performance of H2M based on laboratory and test beam measurements, including a comparison with analog front-end simulations in terms of gain and noise. A particular emphasis is placed on backside thinning in order to reduce material budget, down to a total chip thickness of \SI{21}{\micro\meter} for which no degradation in MIP detection performance is observed. For all investigated samples, a MIP detection efficiency above \SI{99}{\%} is achieved below a threshold of approximately 205 electrons. At this threshold, the fake-hit rate corresponds to a matrix occupancy of fewer than one pixel per the \SI{500}{\nano\second}~frame. Measurements reveal a non-uniform in-pixel response, attributed to the formation of local potential wells in regions with low electric field. A simulation flow combining technology computer-aided design, Monte Carlo, and circuit simulations is used to investigate and describe this behavior, and is applied to develop mitigation strategies for future chip submissions with similar features.

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arXiv2025

Further Characterisation of Digital Pixel Test Structures Implemented in a 65 nm CMOS Process

The next generation of MAPS for future tracking detectors will have to meet stringent requirements placed on them. One such detector is the ALICE ITS3 that aims to be very light at 0.07% X/X$_{0}$ per layer and have a low power consumption in the active area of 40 mW/cm$^{2}$ by implementing wafer-scale MAPS bent into cylindrical half layers. To address these challenging requirements, the ALICE ITS3 project, in conjunction with the CERN EP R&D on monolithic pixel sensors, proposed the Tower Partners Semiconductor Co. 65 nm CMOS process as the starting point for the sensor. After the initial results confirmed the detection efficiency and radiation hardness, the choice of the technology was solidified by demonstrating the feasibility of operating MAPS in low-power consumption regimes, < 50 mW/cm$^{2}$, while maintaining high-quality performance. This was shown through a detailed characterisation of the Digital Pixel Test Structure (DPTS) prototype exposed to X-rays and ionising beams, and the results are presented in this article. Additionally, the sensor was further investigated through studies of the fake-hit rate, the linearity of the front-end in the range 1.7-28 keV, the performance after ionising irradiation, and the detection efficiency of inclined tracks in the range 0-45$^\circ$.

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arXiv2025

Impact of the circuit layout on the charge collection in a monolithic pixel sensor

CERN's strategic R&D programme on technologies for future experiments recently started investigating the TPSCo 65nm ISC CMOS imaging process for monolithic active pixels sensors for application in high energy physics. In collaboration with the ALICE experiment and other institutes, several prototypes demonstrated excellent performance, qualifying the technology. The Hybrid-to-Monolithic (H2M), a new test-chip produced in the same process but with a larger pixel pitch than previous prototypes, exhibits an unexpected asymmetric efficiency pattern. This contribution describes a simulation procedure combining TCAD, Monte Carlo and circuit simulations to model and understand this effect. It proved able to reproduce measurement results and attribute the asymmetric efficiency drop to a slow charge collection due to low amplitude potential wells created by the circuitry layout and impacting efficiency via ballistic deficit.

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arXiv2025

The H2M Monolithic Active Pixel Sensor -- characterizing non-uniform in-pixel response in a 65 nm CMOS imaging technology

The high energy physics community recently gained access to the TPSCo 65 nm ISC (Image Sensor CMOS), which enables a higher in-pixel logic density in monolithic active pixel sensors (MAPS) compared to processes with larger feature sizes. To explore this novel technology, the Hybrid-to-Monolithic (H2M) test chip has been designed and manufactured. The design followed a digital-on-top design workflow and ports a hybrid pixel-detector architecture, with digital pulse processing in each pixel, into a monolithic chip. The chip matrix consists of 64$\times$16 square pixels with a size of 35$\times$35 um2, and a total active area of approximately 1.25 um2. The chip has been successfully integrated into the Caribou DAQ system. It is fully functional, and the measured threshold dispersion and noise agree with the expectation from front-end simulations. However, a non-uniform in-pixel response related to the size and location of the n-wells in the analog circuitry has been observed in test beam measurements and will be discussed in this contribution. This asymmetry in the pixel response, enhanced by the 35 um pixel pitch - larger than in other prototypes - and certain features of the readout circuit, has not been observed in prototypes with smaller pixel pitches in this technology.

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arXiv2025

Transient studies using a TCAD and Allpix Squared combination approach

The goal of the TANGERINE project is to develop the next generation of monolithic silicon pixel detectors using a 65 nm CMOS imaging process, which offers a higher logic density and overall lower power consumption compared to previously used processes. A combination of Technology Computer-Aided Design (TCAD) and Monte Carlo (MC) simulations is used to understand the physical processes within the sensing element and thus the overall performance of the pixel detector. The response of the sensors can then be tested in laboratory and test beam facilities and compared to simulation results. Transient simulations allow for studying the response of the sensor as a function of time, such as the signal produced after a charged particle passes through the sensor. The study of these signals is important to understand the magnitude and timing of the response from the sensors and improve upon them. While TCAD simulations are accurate, the time required to produce a single pulse is large compared to a combination of MC and TCAD simulations. In this work, a validation of the transient simulation approach and studies on charge collection are presented.

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arXiv2025

Caribou - A versatile data acquisition system for silicon pixel detector prototyping

Caribou is a versatile data acquisition system used in multiple collaborative frameworks (CERN EP R&D, DRD3, AIDAinnova, Tangerine) for laboratory and test-beam qualification of novel silicon pixel detector prototypes. The system is built around a common hardware, firmware and software stack shared accross different projects, thereby drastically reducing the development effort and cost. It consists of a custom Control and Readout (CaR) board and a commercial Xilinx Zynq System-on-Chip (SoC) platform. The SoC platform runs a full Yocto distribution integrating the custom software framework (Peary) and a custom FPGA firmware built within a common firmware infrastructure (Boreal). The CaR board provides a hardware environment featuring various services such as powering, slow-control, and high-speed data links for the target detector prototype. Boreal and Peary, in turn, offer firmware and software architectures that enable seamless integration of control and readout for new devices. While the first version of the system used a SoC platform based on the ZC706 evaluation board, migration to a Zynq UltraScale+ architecture is progressing towards the support of the ZCU102 board and the ultimate objective of integrating the SoC functionality directly into the CaR board, eliminating the need for separate evaluation boards. This paper describes the Caribou system, focusing on the latest project developments and showcasing progress and future plans across its hardware, firmware, and software components.

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arXiv2024

Laboratory and beam-test performance study of a 55$~\mu$m pitch iLGAD sensor bonded to a Timepix3 readout chip

This contribution reports on characterisation results of a large-area (2$~\mathrm{cm}^2$) small pitch (55$~\mu$m) inverse Low-Gain Avalanche Detector (iLGAD), bonded to a Timepix3 readout chip. The ilGAD sensors were produced by Micron Semiconductor Ltd with the goal to obtain good gain uniformity and maximise the fill-factor -- an issue present with standard small-pitch LGAD designs. We have conducted detailed performance evaluations using both X-ray calibrations and beam tests. An X-ray fluorescence setup has been used to obtain energy calibration and to identify the optimal operating settings of the new devices, whereas the extensive beam tests allowed for a detailed evaluation of the detector performance. The beam-tests were performed at the CERN SPS North Area H6 beamline, using a 120 GeV/c pion beam. The reference tracking and time-stamping is achieved by a Timepix3-based beam telescope setup. The results show a gain of around 5 with very good uniformity, measured across the whole gain area, as well as a hit time resolution down to 1.3 ns without correcting for the time-walk effects. Furthermore, it is shown that the gain opens the possibility of a good X-ray energy resolution down to 4.5 keV.

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arXiv2024

Characterisation of analogue Monolithic Active Pixel Sensor test structures implemented in a 65 nm CMOS imaging process

Analogue test structures were fabricated using the Tower Partners Semiconductor Co. CMOS 65 nm ISC process. The purpose was to characterise and qualify this process and to optimise the sensor for the next generation of Monolithic Active Pixels Sensors for high-energy physics. The technology was explored in several variants which differed by: doping levels, pixel geometries and pixel pitches (10-25 $\mu$m). These variants have been tested following exposure to varying levels of irradiation up to 3 MGy and $10^{16}$ 1 MeV n$_\text{eq}$ cm$^{-2}$. Here the results from prototypes that feature direct analogue output of a 4$\times$4 pixel matrix are reported, allowing the systematic and detailed study of charge collection properties. Measurements were taken both using $^{55}$Fe X-ray sources and in beam tests using minimum ionizing particles. The results not only demonstrate the feasibility of using this technology for particle detection but also serve as a reference for future applications and optimisations.

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arXiv2024

Simulations and Performance Studies of a MAPS in 65 nm CMOS Imaging Technology

Monolithic active pixel sensors (MAPS) produced in a 65 nm CMOS imaging technology are being investigated for applications in particle physics. The MAPS design has a small collection electrode characterized by an input capacitance of ~fF, granting a high signal-to-noise ratio and low power consumption. Additionally, the 65 nm CMOS imaging technology brings a reduction in material budget and improved logic density of the readout circuitry, compared to previously studied technologies. Given these features, this technology was chosen by the TANGERINE project to develop the next generation of silicon pixel sensors. The sensor design targets temporal and spatial resolutions compatible with the requirements for a vertex detector at future lepton colliders. Simulations and test-beam characterization of technology demonstrators have been carried out in close collaboration with the CERN EP R&D program and the ALICE ITS3 upgrade. TCAD device simulations using generic doping profiles and Monte Carlo simulations have been used to build an understanding of the technology and predict the performance parameters of the sensor. Technology demonstrators of a 65 nm CMOS MAPS with a small collection electrode have been characterized in laboratory and test-beam facilities by studying performance parameters such as cluster size, charge collection, and efficiency. This work compares simulation results to test-beam data. The experimental results establish this technology as a promising candidate for a vertex detector at future lepton colliders and give valuable information for improving the simulation approach.

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arXiv2023

Test-beam Performance Results of the FASTPIX Sub-Nanosecond CMOS Pixel Sensor Demonstrator

Within the ATTRACT FASTPIX project, a monolithic pixel sensor demonstrator chip has been developed in a modified 180 nm CMOS imaging process technology, targeting sub-nanosecond timing precision for single ionising particles. It features a small collection electrode design on a 25 micrometers-thick epitaxial layer and contains 32 mini matrices of 68 hexagonal pixels each, with pixel pitches ranging from 8.66 to 20 micrometers. Four pixels are transmitting an analog output signal and 64 are transmitting binary hit information. Various design variations are explored, aiming at accelerating the charge collection and making the timing of the charge collection more uniform over the pixel area. Signal treatment of the analog waveforms, as well as reconstruction of digital position, time and charge information, is carried out off-chip. This contribution introduces the design of the sensor and readout system and presents performance results for various pixel designs achieved in recent test beam measurements with external tracking and timing reference detectors. A time resolution below 150 ps is obtained at full efficiency for all pixel pitches.

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arXiv2023

Developing a Monolithic Silicon Sensor in a 65 nm CMOS Imaging Technology for Future Lepton Collider Vertex Detectors

Monolithic CMOS sensors in a 65 nm imaging technology are being investigated by the CERN EP Strategic R&D Programme on Technologies for Future Experiments for an application in particle physics. The appeal of monolithic detectors lies in the fact that both sensor volume and readout electronics are integrated in the same silicon wafer, providing a reduction in production effort, costs and scattering material. The Tangerine Project WP1 at DESY participates in the Strategic R&D Programme and is focused on the development of a monolithic active pixel sensor with a time and spatial resolution compatible with the requirements for a future lepton collider vertex detector. By fulfilling these requirements, the Tangerine detector is suitable as well to be used as telescope planes for the DESY-II Test Beam facility. The project comprises all aspects of sensor development, from the electronics engineering and the sensor design using simulations, to laboratory and test beam investigations of prototypes. Generic TCAD Device and Monte-Carlo simulations are used to establish an understanding of the technology and provide important insight into performance parameters of the sensor. Testing prototypes in laboratory and test beam facilities allows for the characterization of their response to different conditions. By combining results from all these studies it is possible to optimize the sensor layout. This contribution presents results from generic TCAD and Monte-Carlo simulations, and measurements performed with test chips of the first sensor submission.

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arXiv2022

Digital Pixel Test Structures implemented in a 65 nm CMOS process

The ALICE ITS3 (Inner Tracking System 3) upgrade project and the CERN EP R&D on monolithic pixel sensors are investigating the feasibility of the Tower Partners Semiconductor Co. 65 nm process for use in the next generation of vertex detectors. The ITS3 aims to employ wafer-scale Monolithic Active Pixel Sensors thinned down to 20 to 40 um and bent to form truly cylindrical half barrels. Among the first critical steps towards the realisation of this detector is to validate the sensor technology through extensive characterisation both in the laboratory and with in-beam measurements. The Digital Pixel Test Structure (DPTS) is one of the prototypes produced in the first sensor submission in this technology and has undergone a systematic measurement campaign whose details are presented in this article. The results confirm the goals of detection efficiency and non-ionising and ionising radiation hardness up to the expected levels for ALICE ITS3 and also demonstrate operation at +20 C and a detection efficiency of 99% for a DPTS irradiated with a dose of $10^{15}$ 1 MeV n$_{\mathrm{eq}}/$cm$^2$. Furthermore, spatial, timing and energy resolutions were measured at various settings and irradiation levels.

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arXiv2022

Status and recent extensions of the Caribou DAQ System for picosecond timing

Caribou is a flexible open-source DAQ system developed and used within several collaborative frameworks (CERN EP R&D, RD50, AIDAinnova) for laboratory and high-rate beam tests and easy integration of new silicon-pixel detector prototypes. It uses common hardware, firmware and software components that are shared across different projects, thereby reducing the development effort and cost for such readout systems significantly. This contribution introduces the FASTPIX, APTS and DPTS detectors recently integrated in Caribou and their requirements in terms of waveform sampling and timing of digital pulses. A Time-to-Digital-Converter implemented in the Caribou FPGA was developed to overcome the limitations of the previously used oscilloscope-based readout. It allows for precision timing over large time spans required for the Time-of-Arrival, Time-over-Threshold, and position encoding used in the FASTPIX and DPTS test chips with asynchronous digital readout. A time resolution after calibration of better than 10 ps is achieved.

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arXiv2022

Development of novel single-die hybridisation processes for small-pitch pixel detectors

Hybrid pixel detectors require a reliable and cost-effective interconnect technology adapted to the pitch and die sizes of the respective applications. During the ASIC and sensor R\&D phase, especially for small-scale applications, such interconnect technologies need to be suitable for the assembly of single dies, typically available from Multi-Project-Wafer submissions. Within the CERN EP R&D programme and the AIDAinnova collaboration, innovative hybridisation concepts targeting vertex-detector applications at future colliders are under development. Recent results of two novel interconnect methods for pixel pitches of 25um and 55um are presented in this contribution -- an industrial fine-pitch SnAg solder bump-bonding process adapted to single-die processing using support wafers, as well as a newly developed in-house single-die interconnection process based on ACF. The fine-pitch bump-bonding process is qualified with hybrid assemblies from a recent bonding campaign at Frauenhofer IZM. Individual CLICpix2 ASICs with 25um pixel pitch were bump-bonded to active-edge silicon sensors with thicknesses ranging from 50um to 130um. The device characterisation was conducted in the laboratory as well as during a beam test campaign at the CERN SPS beam-line, demonstrating an interconnect yield of about 99.7%. The ACF interconnect technology replaces the solder bumps by conductive micro-particles embedded in an epoxy film. The electro-mechanical connection between the sensor and ASIC is achieved via thermocompression of the ACF using a flip-chip device bonder. The required pixel pad topology is achieved with an in-house ENIG plating process. This newly developed ACF hybridisation process is first qualified with the Timepix3 ASICs and sensors with 55um pixel pitch. The technology can be also used for ASIC-PCB/FPC integration, replacing wire bonding or large-pitch solder bumping techniques.

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arXiv2022

Comparison of different sensor thicknesses and substrate materials for the monolithic small collection-electrode technology demonstrator CLICTD

Small collection-electrode monolithic CMOS sensors profit from a high signal-to-noise ratio and a small power consumption, but have a limited active sensor volume due to the fabrication process based on thin high-resistivity epitaxial layers. In this paper, the active sensor depth is investigated in the monolithic small collection-electrode technology demonstrator CLICTD. Charged particle beams are used to study the charge-collection properties and the performance of devices with different thicknesses both for perpendicular and inclined particle incidence. In CMOS sensors with a high-resistivity Czochralski substrate, the depth of the sensitive volume is found to increase by a factor two in comparison with standard epitaxial material and leads to significant improvements in the hit-detection efficiency and the spatial and time resolution.

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arXiv2022

Transient Monte Carlo Simulations for the Optimisation and Characterisation of Monolithic Silicon Sensors

An ever-increasing demand for high-performance silicon sensors requires complex sensor designs that are challenging to simulate and model. The combination of electrostatic finite element simulations with a transient Monte Carlo approach provides simultaneous access to precise sensor modelling and high statistics. The high simulation statistics enable the inclusion of Landau fluctuations and production of secondary particles, which offers a realistic simulation scenario. The transient simulation approach is an important tool to achieve an accurate time-resolved description of the sensor, which is crucial in the face of novel detector prototypes with increasingly precise timing capabilities. The simulated time resolution as a function of operating parameters as well as the full transient pulse can be monitored and assessed, which offers a new perspective on the optimisation and characterisation of silicon sensors. In this paper, a combination of electrostatic finite-element simulations using 3D TCAD and transient Monte Carlo simulations with the Allpix Squared framework are presented for a monolithic CMOS pixel sensor with a small collection diode, that is characterised by a highly inhomogeneous, complex electric field. The results are compared to transient 3D TCAD simulations that offer a precise simulation of the transient behaviour but long computation times. Additionally, the simulations are benchmarked against test-beam data and good agreement is found for the performance parameters over a wide range of different operation conditions.

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