arXiv subjects

Walter Snoeys

Publications and source records attributed to Walter Snoeys.

At least 19 recordsLinked to original sources

arXiv2026

A Data-Driven Fast Simulation Approach for MAPS-based Detectors and their Optimization

A parametric simulation tool for pixel sensors is presented. A realistic pixel response is simulated purely based on measurement input, without requiring detailed knowledge of the underlying manufacturing process. As such, it provides an efficient alternative to the use of Technology Computer-Aided Design simulations, which typically depend on proprietary process information. Due to its parametric approach, the package is fast and thus particularly useful for larger detector systems and high hit rate environments. This work presents measurements, simulation and its validation for the MALTA2 sensor. It is a small collection electrode monolithic active pixel sensor produced in the Tower 180nm Complementary Metal-Oxide-Semiconductor imaging process. Modifications to the sensor's periphery, mainly in the hit merger, are studied in order to optimize the performance for tracking and calorimetry. This optimization is of special interest as part of the MALTA3 sensor redesign in the 65nm Tower Partners Semiconductor Co. process.

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arXiv2026

A Novel Approach for Fault Detection and Failure Analysis of CMOS Copper Metal Stacks

For the Inner Tracking System 3 (ITS3) upgrade, the ALICE experiment at CERN requires monolithic active pixel sensors of dimensions up to 97~mm$\,\times\,$266~mm, occupying a large fraction of a 300 mm wafer. To manufacture such a wafer-scale device, larger than the single design reticle size, stitching is employed. The MOnolithic Stitched Sensor (MOSS) is a prototype silicon pixel sensor of 14~mm$\,\times\,$259~mm size with the primary goal of understanding the stitching technique and yield. Given the large size, high yield is paramount for the ITS3 sensors, and an in-depth yield characterization was performed on these MOSS sensors. In a collaborative effort, the foundry adapted the metal stack to the requirements of the project, but recurrent fault signatures were discovered with various frequencies across all 20 wafers tested, and correlated through dedicated measurements and analyses. Following these findings, the foundry implemented a mitigation strategy to avoid the issue in the future. This article does not describe process details but concentrates on the measurements and analysis method.

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arXiv2025

Influence of Radiation and AC Coupling on Time Performance of Analog Pixels Test Structures in 65 nm CMOS technology

Monolithic Active Pixel Sensors (MAPS) in advanced CMOS imaging technologies are key to next-generation tracking systems for high-energy physics, where radiation hardness and precise vertex reconstruction are essential. As part of the ALICE ITS3 R&D program in synergy with the CERN R&D, we evaluated the performance of the Analog Pixel Test Structures (APTS) fabricated in the TPSCo 65 nm CMOS imaging process. The prototypes employ 10 um pitch pixels with a fast operational amplifier-based buffering stage at the output, enabling direct characterization of intrinsic sensor response. Beam tests with minimum ionizing particles assessed the timing and charge collection of DC- and AC-coupled designs, including devices exposed to 10^14 NIEL and 10^15 NIEL non ioninsing energy loss. DC-coupled sensors demonstrated stable performance, maintaining time resolution lower than 70 ps and >99% detection efficiency up to 10^15 NIEL. AC-coupled sensors demonstrated a wide operational margin, with efficiencies above 99% for clusterization thresholds below 150 electrons. Even though the AC coupling allows higher reverse bias than DC-coupled sensors, the reduced signal amplitude lowers the signal-to-noise ratio, increasing the jitter contribution. At high reverse bias, the AC-coupled sensors achieve time resolutions comparable to the DC-coupled version, demonstrating the viability of both approaches. These results also suggest that combining the low capacitance of DC-coupled designs with the high-bias capability of AC coupling could further enhance time resolution. These results confirm the suitability of 65 nm MAPS for future collider detectors requiring high radiation tolerance, efficiency, and timing precision.

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arXiv2025

Characterization of the H2M Monolithic CMOS Sensor

The H2M (Hybrid-to-Monolithic) is a monolithic pixel sensor manufactured in a modified \SI{65}{\nano\meter}~CMOS imaging process with a small collection electrode. Its design addresses the challenges of porting an existing hybrid pixel detector architecture into a monolithic chip, using a digital-on-top design methodology, and developing a compact digital cell library. Each square pixel integrates an analog front-end and digital pulse processing with an 8-bit counter within a \SI{35}{\micro\meter}~pitch. This contribution presents the performance of H2M based on laboratory and test beam measurements, including a comparison with analog front-end simulations in terms of gain and noise. A particular emphasis is placed on backside thinning in order to reduce material budget, down to a total chip thickness of \SI{21}{\micro\meter} for which no degradation in MIP detection performance is observed. For all investigated samples, a MIP detection efficiency above \SI{99}{\%} is achieved below a threshold of approximately 205 electrons. At this threshold, the fake-hit rate corresponds to a matrix occupancy of fewer than one pixel per the \SI{500}{\nano\second}~frame. Measurements reveal a non-uniform in-pixel response, attributed to the formation of local potential wells in regions with low electric field. A simulation flow combining technology computer-aided design, Monte Carlo, and circuit simulations is used to investigate and describe this behavior, and is applied to develop mitigation strategies for future chip submissions with similar features.

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arXiv2025

Yield, noise and timing studies of ALICE ITS3 stitched sensor test structures: the MOST

In the LHC long shutdown 3, the ALICE experiment upgrades the inner layers of its Inner Tracker System with three layers of wafer-scale stitched sensors bent around the beam pipe. Two stitched sensor evaluation structures, the MOnolithic Stitched Sensor (MOSS) and MOnolithic Stitched Sensor with Timing (MOST) allow the study of yield dependence on circuit density, power supply segmentation, stitching demonstration for power and data transmission, performance dependence on reverse bias, charge collection performance, parameter uniformity across the chip, and performance of wafer-scale data transmission. The MOST measures 25.9 cm x 0.25 cm, has more than 900,000 pixels of 18x18 $\mu$m$^2$ and emphasizes the validation of pixel circuitry with maximum density, together with a high number of power domains separated by switches allowing to disconnect faulty circuits. It employs 1 Gb/s 26 cm long data transmission using asynchronous, data-driven readout. This readout preserves information on pixel address, time of arrival and time over threshold. In the MOSS, by contrast, regions with different in-pixel densities are implemented to study yield dependence and are read synchronously. MOST test results validated the concept of power domain switching and the data transmission over 26 cm stitched lines which are to be employed on the full-size, full-functionality ITS3 prototype sensor, MOSAIX. Jitter of this transmission is still under study. This proceeding summarizes the performance of the stitched sensor test structures with emphasis on the MOST.

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arXiv2025

X-ray Irradiation Studies on the Monopix DMAPS in 150$\,$nm and 180$\,$nm

Monolithic active pixel sensors with depleted substrates present a promising option for pixel detectors in high-radiation environments. High-resistivity silicon substrates and high bias voltage capabilities in commercial CMOS technologies facilitate depletion of the charge sensitive volume. TJ-Monopix2 and LF-Monopix2 are the most recent large-scale chips in their respective development line, aiming for the ATLAS Inner Tracker outer layer requirements. Those include a tolerance to ionizing radiation of up to 100$\,$Mrad. It was evaluated by irradiating both devices with X-rays to the corresponding ionization dose, showing no significant degradation of the performance at 100$\,$Mrad and continuous operability throughout the irradiation campaign.

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arXiv2025

Further Characterisation of Digital Pixel Test Structures Implemented in a 65 nm CMOS Process

The next generation of MAPS for future tracking detectors will have to meet stringent requirements placed on them. One such detector is the ALICE ITS3 that aims to be very light at 0.07% X/X$_{0}$ per layer and have a low power consumption in the active area of 40 mW/cm$^{2}$ by implementing wafer-scale MAPS bent into cylindrical half layers. To address these challenging requirements, the ALICE ITS3 project, in conjunction with the CERN EP R&D on monolithic pixel sensors, proposed the Tower Partners Semiconductor Co. 65 nm CMOS process as the starting point for the sensor. After the initial results confirmed the detection efficiency and radiation hardness, the choice of the technology was solidified by demonstrating the feasibility of operating MAPS in low-power consumption regimes, < 50 mW/cm$^{2}$, while maintaining high-quality performance. This was shown through a detailed characterisation of the Digital Pixel Test Structure (DPTS) prototype exposed to X-rays and ionising beams, and the results are presented in this article. Additionally, the sensor was further investigated through studies of the fake-hit rate, the linearity of the front-end in the range 1.7-28 keV, the performance after ionising irradiation, and the detection efficiency of inclined tracks in the range 0-45$^\circ$.

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arXiv2025

Impact of the circuit layout on the charge collection in a monolithic pixel sensor

CERN's strategic R&D programme on technologies for future experiments recently started investigating the TPSCo 65nm ISC CMOS imaging process for monolithic active pixels sensors for application in high energy physics. In collaboration with the ALICE experiment and other institutes, several prototypes demonstrated excellent performance, qualifying the technology. The Hybrid-to-Monolithic (H2M), a new test-chip produced in the same process but with a larger pixel pitch than previous prototypes, exhibits an unexpected asymmetric efficiency pattern. This contribution describes a simulation procedure combining TCAD, Monte Carlo and circuit simulations to model and understand this effect. It proved able to reproduce measurement results and attribute the asymmetric efficiency drop to a slow charge collection due to low amplitude potential wells created by the circuitry layout and impacting efficiency via ballistic deficit.

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arXiv2025

The H2M Monolithic Active Pixel Sensor -- characterizing non-uniform in-pixel response in a 65 nm CMOS imaging technology

The high energy physics community recently gained access to the TPSCo 65 nm ISC (Image Sensor CMOS), which enables a higher in-pixel logic density in monolithic active pixel sensors (MAPS) compared to processes with larger feature sizes. To explore this novel technology, the Hybrid-to-Monolithic (H2M) test chip has been designed and manufactured. The design followed a digital-on-top design workflow and ports a hybrid pixel-detector architecture, with digital pulse processing in each pixel, into a monolithic chip. The chip matrix consists of 64$\times$16 square pixels with a size of 35$\times$35 um2, and a total active area of approximately 1.25 um2. The chip has been successfully integrated into the Caribou DAQ system. It is fully functional, and the measured threshold dispersion and noise agree with the expectation from front-end simulations. However, a non-uniform in-pixel response related to the size and location of the n-wells in the analog circuitry has been observed in test beam measurements and will be discussed in this contribution. This asymmetry in the pixel response, enhanced by the 35 um pixel pitch - larger than in other prototypes - and certain features of the readout circuit, has not been observed in prototypes with smaller pixel pitches in this technology.

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arXiv2025

Transient studies using a TCAD and Allpix Squared combination approach

The goal of the TANGERINE project is to develop the next generation of monolithic silicon pixel detectors using a 65 nm CMOS imaging process, which offers a higher logic density and overall lower power consumption compared to previously used processes. A combination of Technology Computer-Aided Design (TCAD) and Monte Carlo (MC) simulations is used to understand the physical processes within the sensing element and thus the overall performance of the pixel detector. The response of the sensors can then be tested in laboratory and test beam facilities and compared to simulation results. Transient simulations allow for studying the response of the sensor as a function of time, such as the signal produced after a charged particle passes through the sensor. The study of these signals is important to understand the magnitude and timing of the response from the sensors and improve upon them. While TCAD simulations are accurate, the time required to produce a single pulse is large compared to a combination of MC and TCAD simulations. In this work, a validation of the transient simulation approach and studies on charge collection are presented.

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arXiv2025

Charge calibration of MALTA2, a radiation hard depleted monolithic active pixel sensor

MALTA2 is a depleted monolithic active pixel sensor (DMAPS) designed for tracking at high rates and typically low detection threshold of $\sim150\,\mathrm{e^-}$. A precise knowledge of the threshold is crucial to understanding the charge collection in the pixel and specifying the environment for sensor application. A simple procedure is developed to calibrate the threshold to unit electrons making use of a dedicated charge injection circuit and an Fe-55 source with dominant charge deposition of $1600\, \mathrm{e^-}$. The injection voltage is determined which corresponds to the injection under Fe-55 exposure and is the basis for charge calibration. The charge injection circuit incorporates a capacitance with design value of $\mathrm{C_{inj}}=$ 230 aF. Experimentally, the average capacitance value for non-irradiated samples is found to be $\mathrm{C_{inj,exp}}=$ 257 aF. The 12 % divergence motivates the need for the presented precise calibration procedure, which is proposed to be performed for each MALTA2 sensor.

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arXiv2024

Characterisation of analogue MAPS produced in the 65 nm TPSCo process

Within the context of the ALICE ITS3 collaboration, a set of MAPS small-scale test structures were developed using the 65 nm TPSCo CMOS imaging process with the upgrade of the ALICE inner tracking system as its primary focus. One such sensor, the Circuit Exploratoire 65 nm (CE-65), and its evolution the CE-65v2, were developed to explore charge collection properties for varying configurations including collection layer process (standard, blanket, modified with gap), pixel pitch (15, 18, \SI{22.5}{\micro\meter}), and pixel geometry (square vs hexagonal/staggered). In this work the characterisation of the CE-65v2 chip, based on $^{55}$Fe lab measurements and test beams at CERN SPS, is presented. Matrix gain uniformity up to the $\mathcal{O}$(5\%) level was demonstrated for all considered chip configurations. The CE-65v2 chip achieves a spatial resolution of under \SI{2}{\micro\meter} during beam tests. Process modifications allowing for faster charge collection and less charge sharing result in decreased spatial resolution, but a considerably wider range of operation, with both the \SI{15}{\micro\meter} and \SI{22.5}{\micro\meter} chips achieving over 99\% efficiency up to a $\sim$180 e$^{-}$ seed threshold. The results serve to validate the 65 nm TPSCo CMOS process, as well as to motivate design choices in future particle detection experiments.

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arXiv2024

Simulating Monolithic Active Pixel Sensors: A Technology-Independent Approach Using Generic Doping Profiles

The optimisation of the sensitive region of CMOS sensors with complex non-uniform electric fields requires precise simulations, and this can be achieved by a combination of electrostatic field simulations and Monte Carlo methods. This paper presents the guiding principles of such simulations, using a CMOS pixel sensor with a small collection electrode and a high-resistivity epitaxial layer as an example. The full simulation workflow is described, along with possible pitfalls and how to avoid them. For commercial CMOS processes, detailed doping profiles are confidential, but the presented method provides an optimisation tool that is sufficiently accurate to investigate sensor behaviour and trade-offs of different sensor designs without knowledge of proprietary information. The workflow starts with detailed electric field finite element method simulations in TCAD, using generic doping profiles. Examples of the effect of varying different parameters of the simulated sensor are shown, as well as the creation of weighting fields, and transient pulse simulations. The fields resulting from TCAD simulations can be imported into the Allpix Squared Monte Carlo simulation framework, which enables high-statistics simulations, including modelling of stochastic fluctuations from the underlying physics processes of particle interaction. Example Monte Carlo simulation setups are presented and the different parts of a simulation chain are described. Simulation studies from small collection electrode CMOS sensors are presented, and example results are shown for both single sensors and multiple sensors in a test beam telescope configuration. The studies shown are those typically performed on sensor prototypes in test beam campaigns, and a comparison is made to test beam data, showing a maximum deviation of 4% and demonstrating that the approach is viable for generating realistic results.

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arXiv2024

Time performance of Analog Pixel Test Structures with in-chip operational amplifier implemented in 65 nm CMOS imaging process

In the context of the CERN EP R&D on monolithic sensors and the ALICE ITS3 upgrade, the Tower Partners Semiconductor Co (TPSCo) 65 nm process has been qualified for use in high energy physics, and adopted for the ALICE ITS3 upgrade. An Analog Pixel Test Structure (APTS) featuring fast per pixel operational-amplifier-based buffering for a small matrix of four by four pixels, with a sensor with a small collection electrode and a very non-uniform electric field, was designed to allow detailed characterization of the pixel performance in this technology. Several variants of this chip with different pixel designs have been characterized with a (120 GeV/$c$) positive hadron beam. This result indicates that the APTS-OA prototype variants with the best performance achieve a time resolution of 63 ps with a detection efficiency exceeding 99% and a spatial resolution of 2 $\mu$m, highlighting the potential of TPSCo 65nm CMOS imaging technology for high-energy physics and other fields requiring precise time measurement, high detection efficiency, and excellent spatial resolution.

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arXiv2024

Characterisation of analogue Monolithic Active Pixel Sensor test structures implemented in a 65 nm CMOS imaging process

Analogue test structures were fabricated using the Tower Partners Semiconductor Co. CMOS 65 nm ISC process. The purpose was to characterise and qualify this process and to optimise the sensor for the next generation of Monolithic Active Pixels Sensors for high-energy physics. The technology was explored in several variants which differed by: doping levels, pixel geometries and pixel pitches (10-25 $μ$m). These variants have been tested following exposure to varying levels of irradiation up to 3 MGy and $10^{16}$ 1 MeV n$_\text{eq}$ cm$^{-2}$. Here the results from prototypes that feature direct analogue output of a 4$\times$4 pixel matrix are reported, allowing the systematic and detailed study of charge collection properties. Measurements were taken both using $^{55}$Fe X-ray sources and in beam tests using minimum ionizing particles. The results not only demonstrate the feasibility of using this technology for particle detection but also serve as a reference for future applications and optimisations.

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arXiv2024

Simulations and Performance Studies of a MAPS in 65 nm CMOS Imaging Technology

Monolithic active pixel sensors (MAPS) produced in a 65 nm CMOS imaging technology are being investigated for applications in particle physics. The MAPS design has a small collection electrode characterized by an input capacitance of ~fF, granting a high signal-to-noise ratio and low power consumption. Additionally, the 65 nm CMOS imaging technology brings a reduction in material budget and improved logic density of the readout circuitry, compared to previously studied technologies. Given these features, this technology was chosen by the TANGERINE project to develop the next generation of silicon pixel sensors. The sensor design targets temporal and spatial resolutions compatible with the requirements for a vertex detector at future lepton colliders. Simulations and test-beam characterization of technology demonstrators have been carried out in close collaboration with the CERN EP R&D program and the ALICE ITS3 upgrade. TCAD device simulations using generic doping profiles and Monte Carlo simulations have been used to build an understanding of the technology and predict the performance parameters of the sensor. Technology demonstrators of a 65 nm CMOS MAPS with a small collection electrode have been characterized in laboratory and test-beam facilities by studying performance parameters such as cluster size, charge collection, and efficiency. This work compares simulation results to test-beam data. The experimental results establish this technology as a promising candidate for a vertex detector at future lepton colliders and give valuable information for improving the simulation approach.

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arXiv2024

Cross talk of a large-scale depleted monolithic active pixel sensor (DMAPS) in 180 nm CMOS technology

Monolithic pixel detectors combine readout electronics and sensor in a single entity of silicon, which simplifies the production procedure and lowers the material budget compared to conventional hybrid pixel detector concepts. Benefiting from the advances in commercial CMOS processes towards large biasing voltage capabilities and the increasing availability of high-resistivity substrates, depleted monolithic active pixel sensors (DMAPS) are able to cope with the high-rate and high-radiation environments faced in modern high-energy physics experiments. TJ-Monopix2 is the latest iteration of a DMAPS development line designed in 180 nm TowerSemicondutor technology, which features a large scale (2 x 2) cm$^2$ chip divided into (512 x 512) pixels with a pitch of (33 x 33) um$^2$. All in-pixel electronics are separated from its small collection electrode and process modifications are implemented to improve charge collection efficiency especially after irradiation. The latest laboratory measurements and investigations of a threshold variation observed for TJ-Monopix2 in typical operating conditions are presented.

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arXiv2023

Test-beam Performance Results of the FASTPIX Sub-Nanosecond CMOS Pixel Sensor Demonstrator

Within the ATTRACT FASTPIX project, a monolithic pixel sensor demonstrator chip has been developed in a modified 180 nm CMOS imaging process technology, targeting sub-nanosecond timing precision for single ionising particles. It features a small collection electrode design on a 25 micrometers-thick epitaxial layer and contains 32 mini matrices of 68 hexagonal pixels each, with pixel pitches ranging from 8.66 to 20 micrometers. Four pixels are transmitting an analog output signal and 64 are transmitting binary hit information. Various design variations are explored, aiming at accelerating the charge collection and making the timing of the charge collection more uniform over the pixel area. Signal treatment of the analog waveforms, as well as reconstruction of digital position, time and charge information, is carried out off-chip. This contribution introduces the design of the sensor and readout system and presents performance results for various pixel designs achieved in recent test beam measurements with external tracking and timing reference detectors. A time resolution below 150 ps is obtained at full efficiency for all pixel pitches.

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