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At least 253 records · Page 14Linked to original sources

High Q-factor CMOS-MEMS inductor

This study investigates a high Q-factor spiral inductor fabricated by the CMOS (complementary metal oxide semiconductor) process and a post-process. The spiral inductor is manufactured on silicon substrate using the 0.35 micrometers CMOS process. In order to reduce the substrate loss and enhance the Q-factor of the inductor, silicon substrate under the inductor is removed using a post-process. The post-process uses RIE (reactive ion etching) to etch the sacrificial layer of silicon dioxide, and then TMAH (tetra methyl ammonium hydroxide) is employed to remove the underlying silicon substrate and obtain the suspended spiral inductor. The advantage of the post process is compatible with the CMOS process. The Agilent 8510C network analyzer and a Cascade probe station are used to measure the performances of the spiral inductor. Experiments indicate that the spiral inductor has a Q-factor of 15 at 11 GHz, an inductance of 4 nH at 25.5 GHz and a self-resonance frequency of about 27 GHz.

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Copper Electrodeposition for 3D Integration

Two dimensional (2D) integration has been the traditional approach for IC integration. Due to increasing demands for providing electronic devices with superior performance and functionality in more efficient and compact packages, has driven the semiconductor industry to develop more advanced packaging technologies. Three-dimensional (3D) approaches address both miniaturization and integration required for advanced and portable electronic products. Vertical integration proved to be essential in achieving a greater integration flexibility of disparate technologies, reason for which a general trend of transition from 2D to 3D integration is currently being observed in the industry. 3D chip integration using through silicon via (TSV) copper is considered one of the most advanced technologies among all different types of 3D packaging technologies. Copper electrodeposition is one of technologies that enable the formation of TSV structures. Because of its well-known application for copper damascene, it was believed that its transfer to filling TSV vias would be easily adopted. However, as any new technology at its beginning, there are several challenges that need to be addressed and resolved before becoming a fully mature technology. This paper will address the TSV fill processes using copper electrodeposition, the advantages as well as difficulties associated with this technology and approaches taken to overcome them. Electrochemical characterization of the organics behavior and their effect on via filling will be presented. The effect of wafer design on process performance and throughput, including necessary process optimizations that are required for achieving void-free via filling while reducing the processing time, will be discussed.

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Technologies for 3D Heterogeneous Integration

3D-Integration is a promising technology towards higher interconnect densities and shorter wiring lengths between multiple chip stacks, thus achieving a very high performance level combined with low power consumption. This technology also offers the possibility to build up systems with high complexity just by combining devices of different technologies. For ultra thin silicon is the base of this integration technology, the fundamental processing steps will be described, as well as appropriate handling concepts. Three main concepts for 3D integration have been developed at IZM. The approach with the greatest flexibility called Inter Chip Via - Solid Liquid Interdiffusion (ICV-SLID) is introduced. This is a chip-to-wafer stacking technology which combines the advantages of the Inter Chip Via (ICV) process and the solid-liquid-interdiffusion technique (SLID) of copper and tin. The fully modular ICV-SLID concept allows the formation of multiple device stacks. A test chip was designed and the total process sequence of the ICV-SLID technology for the realization of a three-layer chip-to-wafer stack was demonstrated. The proposed wafer-level 3D integration concept has the potential for low cost fabrication of multi-layer high-performance 3D-SoCs and is well suited as a replacement for embedded technologies based on monolithic integration. To address yield issues a wafer-level chip-scale handling is presented as well, to select known-good dies and work on them with wafer-level process sequences before joining them to integrated stacks.

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Through Silicon Vias as Enablers for 3D Systems

This special session on 3D TSV's will highlight some of the fabrication processes and used technologies to create vias from the frontside of an active circuit to its backside and potential implementation solutions to form complex systems leveraging these novel possibilities. General techniques for via formation are discussed as well as advanced integration solutions leveraging the power of 3D TSV's.

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Fabrication of 3D Packaging TSV using DRIE

Emerging 3D chips stacking and MEMS/Sensors packaging technologies are using DRIE (Deep Reactive Ion Etching) to etch through-silicon via (TSV) for advanced interconnections. The interconnection step can be done prior to or post CMOS manufacturing, each requiring different etch process performances. A review of the DRIE capability in terms of etching profile, etch rate, etch depth has been carried out. Excellent tool flexibility allows a wide range of basic and complex profiles to be achieved. Unlike other techniques, DRIE has the capability to etch feature sizes ranging from sub-micron to millimeter width. The main specificity of the DRIE is that etch rate is sensitive to the total exposed area and the aspect ratio. For the TSV applications, where the total exposed area is lower than 10%, high etch rates are achievable. A study has also been done to highlight the importance of via profile for the success of the refilling step. In addition, due to the high flexibility of DRIE, we also explore the capability of using this technique for wafer thinning and plasma die separation.

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Study of First-Order Thermal Sigma-Delta Architecture for Convective Accelerometers

This paper presents the study of an original closed-loop conditioning approach for fully-integrated convective inertial sensors. The method is applied to an accelerometer manufactured on a standard CMOS technology using an auto-aligned bulk etching step. Using the thermal behavior of the sensor as a summing function, a first order sigma-delta modulator is built. This "electro-physical" modulator realizes an analog-to-digital conversion of the signal. Besides the feedback scheme should improve the sensor performance.

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High Density Through Silicon Via (TSV)

The Through Silicon Via (TSV) process developed by Silex provides down to 30 micrometers pitch for through wafer connections in up to 600 micrometers thick substrates. Integrated with MEMS designs it enables significantly reduced die size and true "Wafer Level Packaging" - features that are particularly important in consumer market applications. The TSV technology also enables integration of advanced interconnect functions in optical MEMS, sensors and microfluidic devices. In addition the Via technology opens for very interesting possibilities considering integration with CMOS processing. With several companies using the process already today, qualified volume manufacturing in place and a line-up of potential users, the process is becoming a standard in the MEMS industry. We provide a introduction to the via formation process and also present some on the novel solutions made available by the technology.

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Rejection of Power Supply Noise in Wheatstone Bridges : Application to Piezoresistive MEMS

This paper deals with the design of MEMS using piezoresistivity as transduction principle. It is demonstrated that when the sensor topology doesn't allow a perfect matching of strain gauges, the resolution is limited by the ability of the conditioning circuit (typically a Wheatstone bridge) to reject power supply noise. As this ability is strongly reduced when an offset voltage is present at the output of the bridge, the proposed architecture implements a feedback loop to control MOS transistors inserted in the Wheatstone bridge to compensate resistor mismatches. This feedback exhibits a very good offset cancellation and therefore a better resolution is achieved.

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Next Generation of TCAD Environments for MEMS Design

In this paper we present the latest version of the TCAD environment BICEP'S (Braunschweigs Integrated CAD-Environment for Product Planning and Process Simulation). By using a central process database, which allows the exchange of all relevant process data it is able to overcome many of the mentioned obstacles. The database and process planning tool can be used by process developers to document changes in process settings and the influence of such changes on the process result. This information can then be used by the designers to set-up a simulation file for a detailed analysis of the impact of such parameter changes on the requested design. This will be shown by the example of silicon etching using an atomistic etch simulator.

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Noise Analysis and Noise-based Optimization for Resonant MEMS Structures

This paper presents a detailed noise analysis and a noise-based optimization procedure for resonant MEMS structures. A design for high sensitivity of MEMS structures needs to take into account the noise shaping induced by damping phenomena at micro scale. The existing literature presents detailed models for the damping at microscale, but usually neglects them in the noise analysis process, assuming instead a white spectrum approximation for the mechano-thermal noise. The present work extends the implications of the complex gas-solid interaction into the field of noise analysis for mechanical sensors, and provides a semi-automatic procedure for behavioral macromodel extraction and sensor optimization with respect to signal-to-noise ratio.

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Haptic sensing for MEMS with application for cantilever and Casimir effect

This paper presents an implementation of the Cosserat theory into haptic sensing technologies for real-time simulation of microstructures. Cosserat theory is chosen instead of the classical theory of elasticity for a better representation of stress, especially in the nonlinear regime. The use of Cosserat theory leads to a reduction of the complexity of the modelling and thus increases its capability for real time simulation which is indispensable for haptic technologies. The incorporation of Cosserat theory into haptic sensing technology enables the designer to simulate in real-time the components in a virtual reality environment (VRE) which can enable virtual manufacturing and prototyping. The software tool created as a result of this methodology demonstrates the feasibility of the proposed model. As test demonstrators, a cantilever microbeam and microbridge undergoing bending in VRE are presented.

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On-Chip Hotplate for Temperature Control of Cmos Saw Resonators

Due to the sensitivity of the piezoelectric layer in surface acoustic wave (SAW) resonators to temperature, a method of achieving device stability as a function of temperature is required. This work presents the design, modeling and characterization of integrated dual-serpentine polysilicon resistors as a method for temperature control of CMOS SAW resonators. The design employs the oven control temperature stabilization scheme where the device's temperature is elevated to higher than Tmax to maintain constant device temperature. The efficiency of the polysilicon resistor as a heating element was verified through a 1-D partial differential equation model, 3-D CoventorWare finite element simulations and measurements using Compix thermal camera. To verify that the on-chip hotplate is effective as a temperature control method, both DC and RF measurements of the heater together with the resonator were conducted. Experimental results have indicated that the TCF of the CMOS SAW resonator of -97.2 ppm/deg C has been reduced to -23.19 ppm/deg C when heated to 56 deg C.

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Modelling methodology of MEMS structures based on Cosserat theory

Modelling MEMS involves a variety of software tools that deal with the analysis of complex geometrical structures and the assessment of various interactions among different energy domains and components. Moreover, the MEMS market is growing very fast, but surprisingly, there is a paucity of modelling and simulation methodology for precise performance verification of MEMS products in the nonlinear regime. For that reason, an efficient and rapid modelling approach is proposed that meets the linear and nonlinear dynamic behaviour of MEMS systems.

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Low Voltage Totally Free Flexible RF MEMS Switch With Anti-Stiction System

This paper concerns a new design of RF MEMS switch combined with an innovative process which enable low actuation voltage (<5V) and avoid stiction. First, the structure described with principal design issues, the corresponding anti-stiction system is presented and FEM simulations are done. Then, a short description of the process flow based on two non polymer sacrificial layers. Finally, RF measurements are presented and preliminary experimental protocol and results of anti-stiction validation is detailed. Resulting RF performances are -30dB of isolation and -0.45dB of insertion loss at 10 GHz.

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High Quality Factor Silicon Cantilever Driven by PZT Actuator for Resonant Based Mass Detection

A high quality factor (Q-factor) piezoelectric lead zirconat titanate (PZT) actuated single crystal silicon cantilever was proposed in this paper for resonant based ultra-sensitive mass detection. Energy dissipation from intrinsic mechanical loss of the PZT film was successfully compressed by separating the PZT actuator from resonant structure. Excellent Q-factor, which is several times larger than conventional PZT cantilever, was achieved under both atmospheric pressure and reduced pressures. For a 30 micrometer-wide 100 micrometer-long cantilever, Q-factor was measured as high as 1113 and 7279 under the pressure of 101.2 KPa and 35 Pa, respectively. Moreover, it was found that high-mode vibration can be realized by the cantilever for the pursuit of great Q-factor, while support loss became significant because of the increased vibration amplitude at the actuation point. An optimized structure using node-point actuation was suggested then to suppress corresponding energy dissipation.

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A New Four States High Deflection Low Actuation Voltage Electrostatic Mems Switch for RF Applications

This paper presents a new electrostatic MEMS (MicroElectroMechanical System) based on a single high reliability totally free flexible membrane. Using four electrodes, this structure enables four states which allowed large deflections (4$μ$m) with low actuation voltage (7,5V). This design presents also a good contact force and improve the restoring force of the structure. As an example of application, a Single Pole Double Throw (SPDT) for 24GHz applications, based on this design, has been simulated.

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Design and Fabrication of a Novel Micro Electromagnetic Actuator

The present study presents a new micro electromagnetic actuator utilizing a PDMS membrane with a magnet. The actuator is integrated with micro coils to electromagnetically actuate the membrane and results in a large deflection. The micro electromagnetic actuator proposed in this study is easily fabricated and is readily integrated with existing bio-medical chips due to its planar structure.

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Flexible Micro Thermoelectric Generator based on Electroplated Bi2Te3

We present and discuss the fabrication process and the performance of a flexible micro thermoelectric generator with electroplated Bi2Te3 thermocouples in a SU-8 mold. Demonstrator devices generate 278uWcm-2 at dTmeas=40K across the experimental set up. Based on model calculations, a temperature difference of dTG=21.4K across the generator is assumed. Due to the flexible design and the chosen generator materials, the performance stays high even for curved contact surfaces. The measurement results correlate well with the model based design optimization predictions.

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