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arXiv · 2604.12889

Building reliable 3D photonic integrated circuits and cavities at the wafer scale

Yuhao Huang·Yunqi Fu·Yu Xia·Yuemin Li·Zheng Li·Yaoran Huang·Zhaoting Geng·Mingfei Liu·Chao Xiang
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Abstract

Three-dimensional (3D) photonic integrated circuits (PIC) are emerging as an indispensable scheme for high density and multifunctional photonic systems. However, the wafer-scale scaling of PICs towards a 3D configuration is constrained by two key factors: (i) the trade-off between inter-layer taper efficiency and footprint, and (ii) wafer-scale uniformity of inter-layer transition loss. In this work, we introduce etch-back assisted chemical mechanical polishing (E-CMP) to achieve high wafer-scale uniformity of the spacer layer. Moreover, we break the efficiency-footprint trade-off by demonstrating a novel $\kappa$-engineered taper, achieving a reliability metric that is 75\% higher than the traditional linearly tapered structure. Building on these design and fabrication developments, we enable reliable 3D PICs with typical loss of 0.077 and 0.068 dB/cm on two silicon nitride (SiN) waveguide layers and typical 3D transition loss as low as 6 mdB. Furthermore, the low 3D transition loss enables the first class of 3D high-Q optical cavities occupying two distinct device layers, providing new design space for high-Q optical cavities. The scalable fabrication process and design methodology provide routes for wafer-scale reliable 3D PICs that are promising in a series of applications ranging from photonic interconnects and computing networks to high-density photonic sensors and nonlinear photonics.

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Yuhao Huang, Yunqi Fu, Yu Xia, Yuemin Li, Zheng Li, Yaoran Huang, Zhaoting Geng, Mingfei Liu, Chao Xiang. 2026-04-14. Building reliable 3D photonic integrated circuits and cavities at the wafer scale. https://arxiv.org/abs/2604.12889

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