arXiv subjects

Fabrizio Roccaforte

Publications and source records attributed to Fabrizio Roccaforte.

17 recordsLinked to original sources

arXiv2024

Impact of the NO annealing duration on the SiO2/4H-SiC interface properties in lateral MOSFETs: the energetic profile of the near-interface-oxide traps

In this work, the effects of the duration of the post deposition annealing (PDA) in nitric oxide (NO) on the properties of SiO2/4H-SiC interfaces in n-channel lateral MOSFETs are investigated, with a special focus on the modifications of the energy profile of near-interface-oxide traps (NIOTs). For this purpose, the electrical characteristics of lateral MOSFETs were studied in strong inversion conditions, monitoring the threshold voltage variations due to charge trapping effects. To determine the energetic position of the NIOTs with respect of the SiO2 conduction band edge, the Fermi level position in the insulating layer was evaluated by TCAD simulations of the band diagrams. PDAs of the gate oxide of different duration resulted into similar shape of the energetic profile of the traps inside the insulator with respect of the SiO2 conduction band edge, but with different magnitude. Finally, the effective decrease of the insulator traps is demonstrated despite a saturation of the interface state density under prolonged PDAs and in particular the charge trapped at the NIOTs is reduced from 1-2 x 1011 cm-2 down to 3 x 1011 cm-2 varying the PDA duration from 10 up to 120 min in NO at 1175 degree C.

cond-mat.mtrl-sci↗

arXiv2024

Complementary two dimensional carrier profiles of 4H-SiC MOSFETs by Scanning Spreading Resistance Microscopy and Scanning Capacitance Microscopy

This paper reports the results presented in an invited poster during the International Conference on Silicon Carbide and Related Materials (ICSCRM) 2023 held in Sorrento, Italy. The suitability of scanning probe methods based on atomic force microscopy (AFM) measurements is explored to investigate with high spatial resolution the elementary cell of 4H-SiC power MOSFETs. The two-dimensional (2D) cross-sectional maps demonstrated a high spatial resolution of about 5 nm using the SSRM capabilities. Furthermore, the SCM capabilities enabled visualizing the fluctuations of charge carrier concentration across the different parts of the MOSFETs elementary cell.

physics.app-ph↗

arXiv2023

Current transport in Ni Schottky barrier on GaN epilayer grown on free standing substrates

In this paper, the Ni Schottky barrier on GaN epilayer grown on free standing substrates has been characterized. First, transmission electrical microscopy (TEM) images and nanoscale electrical analysis by conductive atomic force microscopy (C-AFM) of the bare material allowed visualizing structural defects in the crystal, as well as local inhomogeneities of the current conduction. The forward current-voltage (I-V) characteristics of Ni/GaN vertical Schottky diodes fabricated on the epilayer gave average values of the Schottky barrier height of 0.79 eV and ideality factor of 1.14. A statistical analysis over a set of diodes, combined with temperature dependence measurements, confirmed the formation of an inhomogeneous Schottky barrier in this material. From a plot of FB versus n, an ideal homogeneous barrier close to 0.9 eV was estimated, similar to that extrapolated by capacitance-voltage (C-V) analysis. Local I-V curves, acquired by means of C-AFM, displayed the inhomogeneous distribution of the onset of current conduction, which in turn resembles the one observed in the macroscopic Schottky diodes. Finally, the reverse characteristic of the diodes fabricated in the defects-free region have been acquired at different temperature and its behaviour has been described by the thermionic field emission (TFE) model.

cond-mat.mtrl-sci↗

arXiv2023

Threshold voltage instability by charge trapping effects in the gate region of p-GaN HEMTs

In this work, the threshold voltage instability of normally-off p-GaN high electron mobility transistors (HEMTs) has been investigated by monitoring the gate current density during device on-state. The origin of the gate current variations under stress has been ascribed to charge trapping occurring at the different interfaces in the metal/p-GaN/AlGaN/GaN system. In particular, depending on the stress bias level, electrons (VG < 6 V) or holes (VG > 6 V) are trapped, causing a positive or negative threshold voltage shift {DVTH, respectively. By monitoring the gate current variations at different temperatures, the activation energies associated to the electrons and holes trapping could be determined and correlated with the presence of nitrogen (electron traps) or gallium (hole traps) vacancies. Moreover, the electrical measurements suggested the generation of a new electron-trap upon long-time bias stress, associated to the creation of crystallographic dislocation-like defects extending across the different interfaces (p-GaN/AlGaN/GaN) of the gate stack.

physics.app-ph↗

arXiv2022

Electrical evolution of W and WC Schottky contacts on 4H-SiC at different annealing temperatures

In this paper, we investigate the electrical evolution of tungsten (W) and tungsten carbide (WC) Schottky contacts on 4H-SiC subjected to thermal treatments at different annealing temperatures from 475 to 700 ° C. For each annealing temperature, the uniformity of the Schottky barrier height (${ϕ_B}$) and ideality factor (n) was monitored by current-voltage (I-V) measurements in forward bias, performed over sets of equivalent diodes. Good values of n (below 1.05) were found for both contacts up to thermal annealing at 700 ° C. On the other hand, the barrier of the two contacts behaves differently. For the W/4H-SiC diode, the ${ϕ_B}$ increases with the annealing temperature (from 1.14 eV at 475 ° C to 1.25 eV at 700 ° C), whereas the Schottky barrier in WC/4H-SiC features a slight reduction already with thermal annealing at 475 ° C, remaining almost constant at around 1.06 eV up to annealing at 700 ° C. A deeper characterization was performed on the 700 ° C-annealed contacts by studying the temperature-dependence of the Schottky parameters by current-voltage-temperature (I-V-T) characterization. The ${ϕ_B}$ and n behaviour with temperature indicates the presence of a nanoscale lateral inhomogeneity for both Schottky contacts, which can be described by Tung's model. Finally, the temperature-dependence of the reverse characteristics could be described by the thermionic field emission model (TFE), accounting for the temperature dependent barrier height determined from forward characterization.

physics.app-ph↗

arXiv2021

Direct atomic layer deposition of ultrathin aluminium oxide on monolayer $MoS_2$ exfoliated on gold: the role of the substrate

In this paper we demonstrated the thermal Atomic Layer Deposition (ALD) growth at 250 °C of highly homogeneous and ultra-thin ($\approx$ 3.6 nm) $Al_2O_3$ films with excellent insulating properties directly onto a monolayer (1L) $MoS_2$ membrane exfoliated on gold. Differently than in the case of 1L $MoS_2$ supported by a common insulating substrate ($Al_2O_3/Si$), a better nucleation process of the high-k film was observed on the 1L $MoS_2/Au$ system since the ALD early stages. Atomic force microscopy analyses showed a $\approx 50\%$ $Al_2O_3$ surface coverage just after 10 ALD cycles, its increasing up to $>90\%$ (after 40 cycles), and an uniform $\approx$ 3.6 nm film, after 80 cycles. The coverage percentage was found to be significantly reduced in the case of 2L $MoS_2/Au$, indicating a crucial role of the interfacial interaction between the aluminum precursor and $MoS_2/Au$ surface. Finally, Raman spectroscopy and PL analyses provided an insight about the role played by the tensile strain and p-type doping of 1L $MoS_2$ induced by the gold substrate on the enhanced high-k nucleation of $Al_2O_3$ thin films. The presently shown high quality ALD growth of high-k $Al_2O_3$ dielectrics on large area 1L $MoS_2$ induced by the Au underlayer can be considered of wide interest for potential device applications based on this material system.

physics.app-ph↗

arXiv2021

Interfacial electrical and chemical properties of deposited SiO2 layers in lateral implanted 4H-SiC MOSFETs subjected to different nitridations

In this paper, SiO2 layers deposited on 4H-SiC and subjected to different post deposition annealing (PDA) in NO and N2O were studied to identify the key factors influencing the channel mobility and threshold voltage stability in 4H-SiC MOSFETs. In particular, PDA in NO gave a higher channel mobility (55 cm2V-1s-1) than PDA in N2O (20 cm2V-1s-1), and the subthreshold behavior of the devices confirmed a lower total amount of interface states for the NO case. This latter could be also deduced from the behavior of the capacitance-voltage characteristics of 4H-SiC MOSFETs measured in gate controlled diode configuration. On the other hand, cyclic gate bias stress measurements allowed to separate the contributions of interface states (Nit) both on the upper and bottom parts of the 4H-SiC band gap and near interface oxide traps (NIOTs) in the two oxides. In particular, it was found that NO annealing reduced the total density of charges trapped at the interface states down to 3 x 1011 cm- 2 and those trapped inside the oxide down to 1 x 1011 cm-2. Electron energy loss spectroscopy demonstrated that the reduction of these traps in the NO annealed sample is due to the lower amounts of sub-stoichiometric silicon oxide (~ 1nm) and carbon-related defects (< 1nm) at the interface, respectively. This correlation represents a further step in the comprehension of the physics of the SiO2/4H-SiC interface explaining the mobility and threshold voltage behavior of 4H-SiC MOSFETs.

cond-mat.mtrl-sci↗

arXiv2021

Ohmic contacts on n-type and p-type cubic silicon carbide (3C-SiC) grown on silicon

This paper is a report on Ohmic contacts on n-type and p-type type cubic silicon carbide (3C-SiC) layers grown on silicon substrates. In particular, the morphological, electrical and structural properties of annealed Ni and Ti/Al/Ni contacts has been studied employing several characterization techniques. Ni films annealed at 950°C form Ohmic contacts on moderately n-type doped 3C-SiC (ND ~ 1x1017cm-3), with a specific contact resistance of 3.7x10-3 Ωcm2. The main phase formed upon annealing in this contact was nickel silicide (Ni2Si), with randomly dispersed carbon in the reacted layer. In the case of a p-type 3C-SiC with a high doping level (NA ~ 5x1019cm-3), Ti/Al/Ni contacts were preferable to Ni ones, as they gave much lower values of the specific contact resistance (1.8x10-5 Ωcm2). Here, an Al3Ni2 layer was formed in the uppermost part of the contact, while TiC was detected at the interface. For this system, a temperature dependent electrical characterization allowed to establish that the thermionic field emission rules the current transport at the interface. All these results can be useful for the further development of a devices technology based on the 3C-SiC polytype.

physics.app-ph↗

arXiv2021

Nanolaminated Al2O3/HfO2 dielectrics for silicon carbide based devices

Nanolaminated Al2O3/HfO2 thin films as well as single Al2O3 and HfO2 layers have been grown as gate dielectrics by Plasma Enhanced Atomic Layer Deposition (PEALD) technique on silicon carbide (4H-SiC) substrates. All the three dielectric films have been deposited at temperature as low as 250°C, with a total thickness of about 30 nm and in particular, the nanolaminated Al2O3/HfO2 films have been fabricated by alternating nanometric Al2O3 and HfO2 layers. The structural characteristics and dielectrical properties of the nanolaminated Al2O3/HfO2 films have been evaluated and compared to those of the parent Al2O3 and HfO2 single layers. Moreover, the structural properties and their evolution upon annealing treatment at 800°C have been investigated as preliminar test for their possible implementation in the device fabrication flow-chart. On the basis of the collected data, the nanolaminated films demonstrated to possess promising dielectric behavior with respect to the simple oxide layers.

physics.app-ph↗

arXiv2021

Effect of high temperature annealing (T > 1650°C) on the morphological and electrical properties of p-type implanted 4H-SiC layers

This work reports on the effect of high temperature annealing on the electrical properties of p-type implanted 4H-SiC. Ion implantations of Aluminium (Al) at different energies (30 - 200 keV) were carried out to achieve 300 nm thick acceptor box profiles with a concentration of about 1020 at/cm3. The implanted samples were annealed at high temperatures (1675-1825 °C). Morphological analyses of the annealed samples revealed only a slight increase of the surface roughness RMS up to 1775°C, while this increase becomes more significant at 1825°C (RMS=1.2nm). Room temperature Hall measurements resulted in a hole concentration in the range 0.65-1.34x1018/cm3 and mobility values in the order of 21-27 cm2V-1s-1. The temperature dependent electrical measurements allowed to estimate an activation energy of the Al-implanted specie of about 110 meV (for the post-implantation annealing at 1675°C) and a fraction of active p-type Al-dopant ranging between 39% and 56%. The results give useful indications for the fabrication of 4H-SiC JBS and MOSFETs.

physics.app-ph↗

arXiv2021

Temperature-dependent Fowler-Nordheim electron barrier height in SiO2/4H-SiC MOS capacitors

This paper reports on the physical and temperature-dependent electrical characterizations of the oxide/semiconductor interface in MOS capacitors with a SiO2 layer deposited on 4H-SiC using dichlorosilane and nitrogen-based vapor precursors. The capacitors, subjected to a standard post deposition annealing process in N2O, exhibited an interface state density Dit = 9.0 x 1011cm-2eV-1 below the conduction band edge. At room temperature, a barrier height (conduction band offset) of 2.8 eV was observed, along with the presence of negative charges in the insulator. The SiO2 insulating properties were evaluated by studying the experimental temperature-dependence of the gate current. In particular, the temperature-dependent electrical measurements showed a negative temperature coefficient of the Fowler-Nordheim electron barrier height (dFB/dT = - 0.98 meV/°C), which was very close to the expected value for an ideal SiO2/4H-SiC system and much lower compared to the values reported for thermally grown SiO2. This smaller dependence of FB on the temperature and the increase of the current level with temperature in the transcharacteristics measured in the relative fabricated MOSFETs represents a clear advantage of our deposited SiO2 for the operation of MOSFET devices at high temperatures.

physics.app-ph↗

arXiv2021

Ni Schottky barrier on heavily doped phosphorous implanted 4H-SiC

The electrical behavior of Ni Schottky barrier formed onto heavily doped (ND>1019 cm-3) n-type phosphorous implanted silicon carbide (4H-SiC) was investigated, with a focus on the current transport mechanisms in both forward and reverse bias. The forward current-voltage characterization of Schottky diodes showed that the predominant current transport is a thermionic-field emission mechanism. On the other hand, the reverse bias characteristics could not be described by a unique mechanism. In fact, under moderate reverse bias, implantation-induced damage is responsible for the temperature increase of the leakage current, while a pure field emission mechanism is approached with bias increasing. The potential application of metal/4H-SiC contacts on heavily doped layers in real devices are discussed.

cond-mat.mtrl-sci↗

arXiv2020

Thermal Annealing Effect on Electrical and Structural Properties of Tungsten Carbide Schottky Contacts on AlGaN/GaN heterostructures

Tungsten carbide (WC) contacts have been investigated as a novel gold-free Schottky metallization for AlGaN/GaN heterostructures. The evolution of the electrical and structural/compositional properties of the WC/AlGaN contact has been monitored as a function of the annealing temperature in the range from 400 to 800°C. The Schottky barrier height ($Φ$B) at WC/AlGaN interface, extracted from the forward current-voltage characteristics of the diode, decreased from 0.8 eV in the as-deposited and 400°C annealed sample, to 0.56 eV after annealing at 800 °C. This large reduction of $Φ$B was accompanied by a corresponding increase of the reverse bias leakage current. Transmission electron microscopy coupled to electron energy loss spectroscopy analyses revealed the presence of oxygen (O) uniformly distributed in the WC layer, both in the as-deposited and 400°C annealed sample. Conversely, oxygen accumulation in a 2-3 nm thin W-O-C layer at the interface with AlGaN was observed after the annealing at 800 °C, as well as the formation of W2C grains within the film (confirmed by X-ray diffraction analyses). The formation of this interfacial W-O-C layer is plausibly the main origin of the decreased $Φ$B and the increased leakage current in the 800°C annealed Schottky diode, whereas the decreased O content inside the WC film can explain the reduced resistivity of the metal layer. The results provide an assessment of the processing conditions for the application of WC as Schottky contact for AlGaN/GaN heterostructures.

physics.app-ph↗

arXiv2020

Electrical properties of inhomogeneous tungsten carbide Schottky barrier on 4H-SiC

In this paper, the electrical behavior of tungsten carbide (WC) Schottky barrier on 4H-SiC was investigated. First, a statistical current-voltage (I-V) analysis in forward bias, performed on a set of equivalent diodes, showed a symmetric Gaussian-like distribution of the barrier heights after annealing at 700°C, where a low Schottky barrier height ($Φ$B=1.05 eV) and an ideality factor n=1.06 were measured. The low value of the barrier height makes such a WC contact an interesting candidate to reduce the conduction losses in 4H-SiC Schottky diodes. A deeper characterization has been carried out, by monitoring the temperature dependence of the I-V characteristics and the behavior of the relevant parameters $Φ$B and n. The increase of the barrier height and decrease of the ideality factor with increasing temperature indicated a lateral inhomogeneity of the WC/4H-SiC Schottky contact, which was described by invoking the Tung's model. Interestingly, the temperature dependence of the leakage current under reverse bias could be described by considering in the thermionic field emission model the temperature dependent barrier height related to the inhomogeneity. These results can be useful to predict the behavior of WC/4H-SiC Schottky diodes under operative conditions.

physics.app-ph↗

arXiv2020

Identification of two trapping mechanisms responsible of the threshold voltage variation in SiO$_2$/4H-SiC MOSFETs

A non-relaxing method based on cyclic gate bias stress is used to probe the interface or near-interface traps in the SiO$_2$/4H-SiC system over the whole 4H-SiC band gap. The temperature dependent instability of the threshold voltage in lateral MOSFETs is investigated and two separated trapping mechanisms were found. One mechanism is nearly temperature independent and it is correlated to the presence of near interface oxide traps that are trapped via tunneling from the semiconductor. The second mechanism, having an activation energy of 0.1 eV, has been correlated to the presence of intrinsic defects at the SiO$_2$/4H-SiC interface.

physics.app-ph↗

arXiv2020

Processing issues in SiC and GaN power devices technology: the cases of 4H-SiC planar MOSFET and recessed hybrid GaN MISHEMT

This paper aims to give a short overview on some relevant processing issues existing in SiC and GaN power devices technology. The main focus is put on the importance of the channel mobility in transistors, which is one of the keys to reduce RON and power dissipation. Specifically, in the case of the 4H-SiC planar MOSFETs the most common solutions and recent trends to improve the channel mobility are presented. In the case of GaN, the viable routes to achieve normally-off HEMTs operation are briefly introduced, giving emphasis to the case of the recessed hybrid MISHEMT.

physics.app-ph↗

arXiv2020

Electron trapping at SiO2/4H-SiC interface probed by transient capacitance measurements and atomic resolution chemical analysis

Studying the electrical and structural properties of the interface of the gate oxide (SiO2) with silicon carbide (4H-SiC) is a fundamental topic, with important implications for understanding and optimizing the performances of metal-oxide-semiconductor field effect transistor (MOSFETs). In this paper, near interface oxide traps (NIOTs) in lateral 4H-SiC MOSFETs were investigated combining transient gate capacitance measurements (C-t) and state of the art scanning transmission electron microscopy in electron energy loss spectroscopy (STEM-EELS) with sub-nm resolution. The C-t measurements as a function of temperature indicated that the effective NIOTs discharge time is temperature independent and electrons from NIOTs are emitted toward the semiconductor via-tunnelling. The NIOTs discharge time was modelled taking into account also the interface state density in a tunnelling relaxation model and it allowed to locate traps within a tunnelling distance up to 1.3nm from the SiO2/4H-SiC interface. On the other hand, sub-nm resolution STEM-EELS revealed the presence of a Non-Abrupt (NA) SiO2/4H-SiC interface. The NA interface shows the re-arrangement of the carbon atoms in a sub-stoichiometric SiOx matrix. A mixed sp2/sp3 carbon hybridization in the NA interface region suggests that the interfacial carbon atoms have lost their tetrahedral SiC coordination.

physics.app-ph↗