arXiv subjects

X. Jehl

Publications and source records attributed to X. Jehl.

At least 19 recordsLinked to original sources

arXiv2025

Kondo cloud conductance in cavity-coupled quantum dots with asymmetric barriers

The Kondo effect emerges when a localized spin is screened by conduction electrons, giving rise to a strongly-correlated many-body ground state. In this work, we investigate this phenomenon in a GaAs/AlGaAs quantum dot, focusing on the spatial extension of the Kondo screening cloud in the electron reservoirs. To probe its properties, the dot is coupled to an electronic Fabry-P\'erot interferometer, enabling controlled modulation of the density of states at the Fermi level. The observation of Kondo temperature oscillations indicates a Kondo screening length comparable to the cavity size. Furthermore, we explore how the coupling asymmetry with the two reservoirs affects both the amplitude and the phase of the conductance oscillations, revealing a subtle interplay between coherent transport and Kondo effect.

cond-mat.str-el↗

arXiv2025

A hole spin resilient to dipole-induced thermal effects

Recent advances in scaling up spin-based quantum processors have revealed unanticipated issues related to thermal effects. Microwave pulses required to manipulate and read the qubits are found to overheat the spins environment, which unexpectedly induces Larmor frequency shifts, reducing thereby gate fidelities. In this study, we shine light on these elusive thermal effects, by experimentally characterizing the temperature dependence of the Larmor frequency for a single hole spin in silicon. Our results unambiguously reveal an electrical origin underlying the thermal susceptibility, stemming from the spin-orbit-induced electric susceptibility. We perform an accurate modeling of the spin electrostatic environment and gyromagnetic properties, allowing us to pinpoint electric dipoles which unfreeze as the temperature increases, as responsible for these frequency shifts. Surprisingly, we find that the thermal susceptibility can be tuned with the magnetic field angle and can even cancel out, unveiling a sweet spot where the hole spin is rendered immune to thermal effects. These findings reveal the microscopic origin of longitudinal thermal susceptibility, providing key insight for the design of thermally robust semiconductor qubits.

cond-mat.mes-hall↗

arXiv2022

A single hole spin with enhanced coherence in natural silicon

Semiconductor spin qubits based on spin-orbit states are responsive to electric field excitation allowing for practical, fast and potentially scalable qubit control. Spin-electric susceptibility, however, renders these qubits generally vulnerable to electrical noise, which limits their coherence time. Here we report on a spin-orbit qubit consisting of a single hole electrostatically confined in a natural silicon metal-oxide-semiconductor device. By varying the magnetic field orientation, we reveal the existence of operation sweet spots where the impact of charge noise is minimized while preserving an efficient electric-dipole spin control. We correspondingly observe an extension of the Hahn-echo coherence time up to 88 $μ$s, exceeding by an order of magnitude the best reported values for hole-spin qubits, and approaching the state-of-the-art for electron spin qubits with synthetic spin-orbit coupling in isotopically-purified silicon. This finding largely enhances the prospects of silicon-based hole spin qubits for scalable quantum information processing.

cond-mat.mes-hall↗

arXiv2021

Compact gate-based read-out of multiplexed quantum devices with a cryogenic CMOS active inductor

In the strive for scalable quantum processors, significant effort is being devoted to the development of cryogenic classical hardware for the control and readout of a growing number of qubits. Here we report on a cryogenic circuit incorporating a CMOS-based active inductor enabling fast impedance measurements with a sensitivity of 10 aF and an input-referred noise of 3.7 aF/sqrt(Hz). This type of circuit is especially conceived for the readout of semiconductor spin qubits. As opposed to commonly used schemes based on dispersive rf reflectometry, which require mm-scale passive inductors, it allows for a markedly reduced footprint (50$μ$m $\times$ 60$μ$m), facilitating its integration in a scalable quantum-classical architecture. In addition, its active inductor results in a resonant circuit with tunable frequency and quality factor, enabling the optimization of readout sensitivity.

quant-ph↗

arXiv2019

Gate reflectometry for probing charge and spin states in linear Si MOS split-gate arrays

We fabricated linear arrangements of multiple splitgate devices along an SOI mesa, thus forming a 2xN array of individually controllable Si quantum dots (QDs) with nearest neighbor coupling. We implemented two different gate reflectometry-based readout schemes to either probe spindependent charge movements by a coupled electrometer with single-shot precision, or directly sense a spin-dependent quantum capacitance. These results bear significance for fast, high-fidelity single-shot readout of large arrays of foundrycompatible Si MOS spin qubits.

cond-mat.mes-hall↗

arXiv2019

Towards scalable silicon quantum computing

We report the efforts and challenges dedicated towards building a scalable quantum computer based on Si spin qubits. We review the advantages of relying on devices fabricated in a thin film technology as their properties can be in situ tuned by the back gate voltage, which prefigures tuning capabilities in scalable qubits architectures.

cond-mat.mes-hall↗

arXiv2019

Si CMOS Platform for Quantum Information Processing

We report the first quantum bit device implemented on a foundry-compatible Si CMOS platform. The device, fabricated using SOI NanoWire MOSFET technology, is in essence a compact two-gate pFET. The qubit is encoded in the spin degree of freedom of a hole Quantum Dot defined by one of the Gates. Coherent spin manipulation is performed by means of an RF E-Field signal applied to the Gate itself.

cond-mat.mes-hall↗

arXiv2019

All-Electrical Control of a Hybrid Electron Spin/Valley Quantum Bit in SOI CMOS Technology

We successfully demonstrated experimentally the electrical-field-mediated control of the spin of electrons confined in an SOI Quantum Dot (QD) device fabricated with a standard CMOS process flow. Furthermore, we show that the Back-Gate control in SOI devices enables switching a quantum bit (qubit) between an electrically-addressable, yet charge noise-sensitive configuration, and a protected configuration.

cond-mat.mes-hall↗

arXiv2019

Control of single spin in CMOS devices and its application for quantum bits

We show how to measure and manipulate a single spin in a CMOS device fabricated in a pre-industrial 300 mm CMOS foundry. The device can be used as a spin quantum bit working at very low temperature. The spin manipulation is done by a microwave electric field applied directly on a gate. The presented results are a proof-of-principle demonstration of the possibility to define qubits by means of conventional industrial fabrication processes.

cond-mat.mes-hall↗

arXiv2019

SOI technology for quantum information processing

We present recent progress towards the implementation of a scalable quantum processor based on fully-depleted silicon-on-insulator (FDSOI) technology. In particular, we discuss an approach where the elementary bits of quantum information - so-called qubits - are encoded in the spin degree of freedom of gate-confined holes in p-type devices. We show how a hole-spin can be efficiently manipulated by means of a microwave excitation applied to the corresponding confining gate. The hole spin state can be read out and reinitialized through a Pauli blockade mechanism. The studied devices are derived from silicon nanowire field-effect transistors. We discuss their prospects for scalability and, more broadly, the potential advantages of FDSOI technology.

cond-mat.mes-hall↗

arXiv2019

Gate-reflectometry dispersive readout and coherent control of a spin qubit in silicon

Silicon spin qubits have emerged as a promising path to large-scale quantum processors. In this prospect, the development of scalable qubit readout schemes involving a minimal device overhead is a compelling step. Here we report the implementation of gate-coupled rf reflectometry for the dispersive readout of a fully functional spin qubit device. We use a p-type double-gate transistor made using industry-standard silicon technology. The first gate confines a hole quantum dot encoding the spin qubit, the second one a helper dot enabling readout. The qubit state is measured through the phase response of a lumped-element resonator to spin-selective interdot tunneling. The demonstrated qubit readout scheme requires no coupling to a Fermi reservoir, thereby offering a compact and potentially scalable solution whose operation may be extended above 1\,K.

cond-mat.mes-hall↗

arXiv2019

Cryogenic characterization of 28nm FD-SOI ring oscillators with energy efficiency optimization

Extensive electrical characterization of ring oscillators (ROs) made in high-$κ$ metal gate 28nm Fully-Depleted Silicon-on- Insulator (FD-SOI) technology is presented for a set of temperatures between 296 and 4.3K. First, delay per stage ($τ_P$), static current ($I_{STAT}$), and dynamic current ($I_{DYN}$) are analyzed for the case of the increase of threshold voltage ($V_{TH}$) observed at low temperature. Then, the same analysis is performed by compensating $V_{TH}$ to a constant, temperature independent value through forward body-biasing (FBB). Energy efficiency optimization is proposed for different supply voltages ($V_{DD}$) in order to find an optimal operating point combining both high RO frequencies and low power dissipation. We show that the Energy-Delay product ($EDP$) can be significantly reduced at low temperature by applying a forward body bias voltage ($V_{FBB}$). We demonstrate that outstanding performance of RO in terms of speed ($τ_P$=37ps) and static power (7nA/stage) can be achieved at 4.3K with $V_{DD}$ reduced down to 0.325V.

physics.app-ph↗

arXiv2019

Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs described with Band Broadening

In the standard MOSFET description of the drain current $I_{D}$ as a function of applied gate voltage $V_{GS}$, the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}$ has a fundamental lower limit as a function of temperature $T$ given by $SS(T) = \ln10~k_BT/e$. However, recent low-temperature studies of different advanced CMOS technologies have reported $SS$(4K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of $SS(T)$ in 28nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying Fermi-Dirac statistics. This results in a subthreshold $I_{D}\sim e^{eV_{GS}/k_BT_0}$ for $T_0=35$K with saturation value $SS(T<T_0) = \ln 10~k_BT_0/e$. The proposed model adequately describes the experimental data of $SS(T)$ from 300 down to 4K using $k_BT_0 \simeq 3$meV for the width of the exponential tail and can also accurately describe $SS(I_{D})$ within the whole subthreshold region. Our analysis allows a direct determination of the technology-dependent band-tail extension forming a crucial element in future compact modeling and design of cryogenic circuits.

cond-mat.mes-hall↗

arXiv2017

Pauli spin blockade in CMOS double quantum dot devices

Silicon quantum dots are attractive candidates for the development of scalable, spin-based qubits. Pauli spin blockade in double quantum dots provides an efficient, temperature independent mechanism for qubit readout. Here we report on transport experiments in double gate nanowire transistors issued from a CMOS process on 300 mm silicon-on-insulator wafers. At low temperature the devices behave as two few-electron quantum dots in series. We observe signatures of Pauli spin blockade with a singlet-triplet splitting ranging from 0.3 to 1.3 meV. Magneto-transport measurements show that transitions which conserve spin are shown to be magnetic-field independent up to B = 6 T.

cond-mat.mes-hall↗

arXiv2016

Design and operation of CMOS-compatible electron pumps fabricated with optical lithography

We report CMOS-compatible quantized current sources (electron pumps) fabricated with nanowires (NWs) on 300 mm SOI wafers. Unlike other Al, GaAs or Si based metallic or semiconductor pumps, the fabrication does not rely on electron-beam lithography. The structure consists of two gates in series on the nanowire and the only difference with the SOI nanowire process lies in long (40 nm) nitride spacers. As a result a single, silicided island gets isolated between the gates and transport is dominated by Coulomb blockade at cryogenic temperatures thanks to the small size and therefore capacitance of this island. Operation and performances comparable to devices featuring e-beam lithography is demonstrated in the non-adiabatic pumping regime, with a pumping frequency up to 300 MHz. We also identify and model signatures of charge traps affecting charge pumping in the adiabatic regime. The availability of quantized current references in a process close to the 28FDSOI technology could trigger new applications for these pumps and allow to cointegrate them with cryogenic CMOS circuits, for instance in the emerging field of interfaces with quantum bits.

cond-mat.mes-hall↗

arXiv2016

A CMOS silicon spin qubit

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot (QD) encoding a hole spin qubit, the second one a QD used for the qubit readout. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. Our result opens a viable path to qubit up-scaling through a readily exploitable CMOS platform.

cond-mat.mes-hall↗

arXiv2015

Electrical control of g-factors in a few-hole silicon nanowire MOSFET

Hole spins in silicon represent a promising yet barely explored direction for solid-state quantum computation, possibly combining long spin coherence, resulting from a reduced hyperfine interaction, and fast electrically driven qubit manipulation. Here we show that a silicon-nanowire field-effect transistor based on state-of-the-art silicon-on-insulator technology can be operated as a few-hole quantum dot. A detailed magnetotransport study of the first accessible hole reveals a g-factor with unexpectedly strong anisotropy and gate dependence. We infer that these two characteristics could enable an electrically-driven g-tensor-modulation spin resonance with Rabi frequencies exceeding several hundred MHz.

cond-mat.mes-hall↗

arXiv2015

Dispersively detected Pauli Spin-Blockade in a Silicon Nanowire Field-Effect Transistor

We report the dispersive readout of the spin state of a double quantum dot formed at the corner states of a silicon nanowire field-effect transistor. Two face-to-face top-gate electrodes allow us to independently tune the charge occupation of the quantum dot system down to the few-electron limit. We measure the charge stability of the double quantum dot in DC transport as well as dispersively via in-situ gate-based radio frequency reflectometry, where one top-gate electrode is connected to a resonator. The latter removes the need for external charge sensors in quantum computing architectures and provides a compact way to readout the dispersive shift caused by changes in the quantum capacitance during interdot charge transitions. Here, we observe Pauli spin-blockade in the high-frequency response of the circuit at finite magnetic fields between singlet and triplet states. The blockade is lifted at higher magnetic fields when intra-dot triplet states become the ground state configuration. A lineshape analysis of the dispersive phase shift reveals furthermore an intradot valley-orbit splitting $Δ_{vo}$ of 145 $μ$eV. Our results open up the possibility to operate compact CMOS technology as a singlet-triplet qubit and make split-gate silicon nanowire architectures an ideal candidate for the study of spin dynamics.

cond-mat.mes-hall↗