arXiv subjects

M. Vinet

Publications and source records attributed to M. Vinet.

At least 19 recordsLinked to original sources

arXiv2023

RF simulation platform of qubit control using FDSOI technology for quantum computing

In this paper, we report on simulations of an Electron Spin Resonance (ESR) RF control line for semiconductor electron spin qubits. The simulation includes both the ESR line characteristics (geometry and configuration, stack and material properties) and the electromagnetic (EM) environment at the vicinity of the qubits such as gates and interconnect network. With the accurate assessment of the magnetic and electric field distribution, we found that the EM environment of the qubits contributes significantly to the ESR line efficiency for spin control characterized by the magnetic over electric field ratio generated at the qubit location.

quant-ph↗

arXiv2023

A new FDSOI spin qubit platform with 40nm effective control pitch

Operating Si quantum dot (QD) arrays requires homogeneous and ultra-dense structures with aggressive gate pitch. Such a density is necessary to separately control the QDs chemical potential (i.e. charge occupation of each QD) from the exchange interaction (i.e. tunnel barriers between each QD). We present here a novel Si quantum device integration that halves the effective gate pitch and provides full controllability in 1D FDSOI QD arrays. The major advantages of this architecture are explored through numerical simulations. Functionality of the fabricated structure is validated via 300K statistical electrical characterization, while tunnel-coupling control is demonstrated at cryogenic temperature.

cond-mat.mes-hall↗

arXiv2022

A quantum dot-based frequency multiplier

Silicon offers the enticing opportunity to integrate hybrid quantum-classical computing systems on a single platform. For qubit control and readout, high-frequency signals are required. Therefore, devices that can facilitate its generation are needed. Here, we present a quantum dot-based radiofrequency multiplier operated at cryogenic temperatures. The device is based on the non-linear capacitance-voltage characteristics of quantum dot systems arising from their low-dimensional density of states. We implement the multiplier in a multi-gate silicon nanowire transistor using two complementary device configurations: a single quantum dot coupled to a charge reservoir and a coupled double quantum dot. We study the harmonic voltage conversion as a function of energy detuning, multiplication factor and harmonic phase noise and find near ideal performance up to a multiplication factor of 10. Our results demonstrate a method for high-frequency conversion that could be readily integrated into silicon-based quantum computing systems and be applied to other semiconductors.

cond-mat.mes-hall↗

arXiv2022

Fast high-fidelity single-shot readout of spins in silicon using a single-electron box

Three key metrics for readout systems in quantum processors are measurement speed, fidelity and footprint. Fast high-fidelity readout enables mid-circuit measurements, a necessary feature for many dynamic algorithms and quantum error correction, while a small footprint facilitates the design of scalable, highly-connected architectures with the associated increase in computing performance. Here, we present two complementary demonstrations of fast high-fidelity single-shot readout of spins in silicon quantum dots using a compact, dispersive charge sensor: a radio-frequency single-electron box. The sensor, despite requiring fewer electrodes than conventional detectors, performs at the state-of-the-art achieving spin read-out fidelity of 99.2% in less than 6 $\mu$s. We demonstrate that low-loss high-impedance resonators, highly coupled to the sensing dot, in conjunction with Josephson parametric amplification are instrumental in achieving optimal performance. We quantify the benefit of Pauli spin blockade over spin-dependent tunneling to a reservoir, as the spin-to-charge conversion mechanism in these readout schemes. Our results place dispersive charge sensing at the forefront of readout methodologies for scalable semiconductor spin-based quantum processors.

cond-mat.mes-hall↗

arXiv2022

A single hole spin with enhanced coherence in natural silicon

Semiconductor spin qubits based on spin-orbit states are responsive to electric field excitation allowing for practical, fast and potentially scalable qubit control. Spin-electric susceptibility, however, renders these qubits generally vulnerable to electrical noise, which limits their coherence time. Here we report on a spin-orbit qubit consisting of a single hole electrostatically confined in a natural silicon metal-oxide-semiconductor device. By varying the magnetic field orientation, we reveal the existence of operation sweet spots where the impact of charge noise is minimized while preserving an efficient electric-dipole spin control. We correspondingly observe an extension of the Hahn-echo coherence time up to 88 $\mu$s, exceeding by an order of magnitude the best reported values for hole-spin qubits, and approaching the state-of-the-art for electron spin qubits with synthetic spin-orbit coupling in isotopically-purified silicon. This finding largely enhances the prospects of silicon-based hole spin qubits for scalable quantum information processing.

cond-mat.mes-hall↗

arXiv2021

Valley population of donor states in highly strained silicon

Strain is extensively used to controllably tailor the electronic properties of materials. In the context of indirect band-gap semiconductors such as silicon, strain lifts the valley degeneracy of the six conduction band minima, and by extension the valley states of electrons bound to phosphorus donors. Here, single phosphorus atoms are embedded in an engineered thin layer of silicon strained to 0.8% and their wave function imaged using spatially resolved spectroscopy. A prevalence of the out-of-plane valleys is confirmed from the real-space images, and a combination of theoretical modelling tools is used to assess how this valley repopulation effect can yield isotropic exchange and tunnel interactions in the $xy$-plane relevant for atomically precise donor qubit devices. Finally, the residual presence of in-plane valleys is evidenced by a Fourier analysis of both experimental and theoretical images, and atomistic calculations highlight the importance of higher orbital excited states to obtain a precise relationship between valley population and strain. Controlling the valley degree of freedom in engineered strained epilayers provides a new competitive asset for the development of donor-based quantum technologies in silicon.

cond-mat.mes-hall↗

arXiv2020

Scaling silicon-based quantum computing using CMOS technology: State-of-the-art, Challenges and Perspectives

Complementary metal-oxide semiconductor (CMOS) technology has radically reshaped the world by taking humanity to the digital age. Cramming more transistors into the same physical space has enabled an exponential increase in computational performance, a strategy that has been recently hampered by the increasing complexity and cost of miniaturization. To continue achieving significant gains in computing performance, new computing paradigms, such as quantum computing, must be developed. However, finding the optimal physical system to process quantum information, and scale it up to the large number of qubits necessary to build a general-purpose quantum computer, remains a significant challenge. Recent breakthroughs in nanodevice engineering have shown that qubits can now be manufactured in a similar fashion to silicon field-effect transistors, opening an opportunity to leverage the know-how of the CMOS industry to address the scaling challenge. In this article, we focus on the analysis of the scaling prospects of quantum computing systems based on CMOS technology.

quant-ph↗

arXiv2020

Spin readout of a CMOS quantum dot by gate reflectometry and spin-dependent tunnelling

Silicon spin qubits are promising candidates for realising large scale quantum processors, benefitting from a magnetically quiet host material and the prospects of leveraging the mature silicon device fabrication industry. We report the measurement of an electron spin in a singly-occupied gate-defined quantum dot, fabricated using CMOS compatible processes at the 300 mm wafer scale. For readout, we employ spin-dependent tunneling combined with a low-footprint single-lead quantum dot charge sensor, measured using radiofrequency gate reflectometry. We demonstrate spin readout in two devices using this technique, obtaining valley splittings in the range 0.5-0.7 meV using excited state spectroscopy, and measure a maximum electron spin relaxation time ($T_1$) of $9 \pm 3$ s at 1 Tesla. These long lifetimes indicate the silicon nanowire geometry and fabrication processes employed here show a great deal of promise for qubit devices, while the spin-readout method demonstrated here is well-suited to a variety of scalable architectures.

cond-mat.mes-hall↗

arXiv2019

Gate reflectometry for probing charge and spin states in linear Si MOS split-gate arrays

We fabricated linear arrangements of multiple splitgate devices along an SOI mesa, thus forming a 2xN array of individually controllable Si quantum dots (QDs) with nearest neighbor coupling. We implemented two different gate reflectometry-based readout schemes to either probe spindependent charge movements by a coupled electrometer with single-shot precision, or directly sense a spin-dependent quantum capacitance. These results bear significance for fast, high-fidelity single-shot readout of large arrays of foundrycompatible Si MOS spin qubits.

cond-mat.mes-hall↗

arXiv2019

Towards scalable silicon quantum computing

We report the efforts and challenges dedicated towards building a scalable quantum computer based on Si spin qubits. We review the advantages of relying on devices fabricated in a thin film technology as their properties can be in situ tuned by the back gate voltage, which prefigures tuning capabilities in scalable qubits architectures.

cond-mat.mes-hall↗

arXiv2019

Si CMOS Platform for Quantum Information Processing

We report the first quantum bit device implemented on a foundry-compatible Si CMOS platform. The device, fabricated using SOI NanoWire MOSFET technology, is in essence a compact two-gate pFET. The qubit is encoded in the spin degree of freedom of a hole Quantum Dot defined by one of the Gates. Coherent spin manipulation is performed by means of an RF E-Field signal applied to the Gate itself.

cond-mat.mes-hall↗

arXiv2019

All-Electrical Control of a Hybrid Electron Spin/Valley Quantum Bit in SOI CMOS Technology

We successfully demonstrated experimentally the electrical-field-mediated control of the spin of electrons confined in an SOI Quantum Dot (QD) device fabricated with a standard CMOS process flow. Furthermore, we show that the Back-Gate control in SOI devices enables switching a quantum bit (qubit) between an electrically-addressable, yet charge noise-sensitive configuration, and a protected configuration.

cond-mat.mes-hall↗

arXiv2019

28nm Fully-Depleted SOI Technology: Cryogenic Control Electronics for Quantum Computing

This paper reports the first cryogenic characterization of 28nm Fully-Depleted-SOI CMOS technology. A comprehensive study of digital/analog performances and body-biasing from room to the liquid helium temperature is presented. Despite a cryogenic operation, effectiveness of body-biasing remains unchanged and provides an excellent $V_{TH}$ controllability. Low-temperature operation enables higher drive current and a largely reduced subthreshold swing (down to 7mV/dec). FDSOI can provide a valuable approach to cryogenic low-power electronics. Applications such as classical control hardware for quantum processors are envisioned.

physics.app-ph↗

arXiv2019

Control of single spin in CMOS devices and its application for quantum bits

We show how to measure and manipulate a single spin in a CMOS device fabricated in a pre-industrial 300 mm CMOS foundry. The device can be used as a spin quantum bit working at very low temperature. The spin manipulation is done by a microwave electric field applied directly on a gate. The presented results are a proof-of-principle demonstration of the possibility to define qubits by means of conventional industrial fabrication processes.

cond-mat.mes-hall↗

arXiv2019

SOI technology for quantum information processing

We present recent progress towards the implementation of a scalable quantum processor based on fully-depleted silicon-on-insulator (FDSOI) technology. In particular, we discuss an approach where the elementary bits of quantum information - so-called qubits - are encoded in the spin degree of freedom of gate-confined holes in p-type devices. We show how a hole-spin can be efficiently manipulated by means of a microwave excitation applied to the corresponding confining gate. The hole spin state can be read out and reinitialized through a Pauli blockade mechanism. The studied devices are derived from silicon nanowire field-effect transistors. We discuss their prospects for scalability and, more broadly, the potential advantages of FDSOI technology.

cond-mat.mes-hall↗

arXiv2019

Fast gate-based readout of silicon quantum dots using Josephson parametric amplification

Spins in silicon quantum devices are promising candidates for large-scale quantum computing. Gate-based sensing of spin qubits offers compact and scalable readout with high fidelity, however further improvements in sensitivity are required to meet the fidelity thresholds and measurement timescales needed for the implementation of fast-feedback in error correction protocols. Here, we combine radio-frequency gate-based sensing at 622 MHz with a Josephson parametric amplifier (JPA), that operates in the 500-800 MHz band, to reduce the integration time required to read the state of a silicon double quantum dot formed in a nanowire transistor. Based on our achieved signal-to-noise ratio (SNR), we estimate that singlet-triplet single-shot readout with an average fidelity of 99.7% could be performed in 1 $\mu$s, well-below the requirements for fault-tolerant readout and 30 times faster than without the JPA. Additionally, the JPA allows operation at a lower RF power while maintaining identical SNR. We determine a noise temperature of 200 mK with a contribution from the JPA (25%), cryogenic amplifier (25%) and the resonator (50%), showing routes to further increase the read-out speed.

cond-mat.mes-hall↗

arXiv2019

Cryogenic characterization of 28nm FD-SOI ring oscillators with energy efficiency optimization

Extensive electrical characterization of ring oscillators (ROs) made in high-$\kappa$ metal gate 28nm Fully-Depleted Silicon-on- Insulator (FD-SOI) technology is presented for a set of temperatures between 296 and 4.3K. First, delay per stage ($\tau_P$), static current ($I_{STAT}$), and dynamic current ($I_{DYN}$) are analyzed for the case of the increase of threshold voltage ($V_{TH}$) observed at low temperature. Then, the same analysis is performed by compensating $V_{TH}$ to a constant, temperature independent value through forward body-biasing (FBB). Energy efficiency optimization is proposed for different supply voltages ($V_{DD}$) in order to find an optimal operating point combining both high RO frequencies and low power dissipation. We show that the Energy-Delay product ($EDP$) can be significantly reduced at low temperature by applying a forward body bias voltage ($V_{FBB}$). We demonstrate that outstanding performance of RO in terms of speed ($\tau_P$=37ps) and static power (7nA/stage) can be achieved at 4.3K with $V_{DD}$ reduced down to 0.325V.

physics.app-ph↗

arXiv2019

Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs described with Band Broadening

In the standard MOSFET description of the drain current $I_{D}$ as a function of applied gate voltage $V_{GS}$, the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}$ has a fundamental lower limit as a function of temperature $T$ given by $SS(T) = \ln10~k_BT/e$. However, recent low-temperature studies of different advanced CMOS technologies have reported $SS$(4K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of $SS(T)$ in 28nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying Fermi-Dirac statistics. This results in a subthreshold $I_{D}\sim e^{eV_{GS}/k_BT_0}$ for $T_0=35$K with saturation value $SS(T<T_0) = \ln 10~k_BT_0/e$. The proposed model adequately describes the experimental data of $SS(T)$ from 300 down to 4K using $k_BT_0 \simeq 3$meV for the width of the exponential tail and can also accurately describe $SS(I_{D})$ within the whole subthreshold region. Our analysis allows a direct determination of the technology-dependent band-tail extension forming a crucial element in future compact modeling and design of cryogenic circuits.

cond-mat.mes-hall↗