arXiv · 1807.10754
Evaluation of Single-Chip, Real-Time Tomographic Data Processing on FPGA - SoC Devices
Abstract
A novel approach to tomographic data processing has been developed and evaluated using the Jagiellonian PET (J-PET) scanner as an example. We propose a system in which there is no need for powerful, local to the scanner processing facility, capable to reconstruct images on the fly. Instead we introduce a Field Programmable Gate Array (FPGA) System-on-Chip (SoC) platform connected directly to data streams coming from the scanner, which can perform event building, filtering, coincidence search and Region-Of-Response (ROR) reconstruction by the programmable logic and visualization by the integrated processors. The platform significantly reduces data volume converting raw data to a list-mode representation, while generating visualization on the fly.
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G. Korcyl, P. Białas, C. Curceanu, E. Czerwiński, K. Dulski, B. Flak, A. Gajos, B. Głowacz, M. Gorgol, B. C. Hiesmayr, B. Jasińska, K. Kacprzak, M. Kajetanowicz, D. Kisielewska, P. Kowalski, T. Kozik, N. Krawczyk, W. Krzemień, E. Kubicz, M. Mohammed, Sz. Niedźwiecki, M. Pawlik-Niedźwiecka, M. Pałka, L. Raczyński, P. Rajda, Z. Rudy, P. Salabura, N. G. Sharma, S. Sharma, R. Y. Shopa, M. Skurzok, M. Silarski, P. Strzempek, A. Wieczorek, W. Wiślicki, R. Zaleski, B. Zgardzińska, M. Zieliński, P. Moskal. 2018-07-26. Evaluation of Single-Chip, Real-Time Tomographic Data Processing on FPGA - SoC Devices. https://doi.org/10.1109/tmi.2018.2837741
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