TCAD Simulation of Stitching for Passive CMOS Strip Detectors

Abstract

Most of the tracking detectors for high energy particle experiments are filled with silicon detectors since they are radiation hard, they can give very small spatial resolution and they can take advantage of the silicon electronics foundries developments and production lines. Strip detectors are very useful to cover large areas for tracking purposes, while consuming less power per area compared to pixel sensors. The majority of particle physics experiments use conventional silicon strip detectors fabricated in foundries that do not use stitching, relying on a very small number of foundries worldwide that can provide large amounts of strip detectors. Fabricating strip detectors in a CMOS foundry opens the possibility to use more foundries and to include active elements in the strips for future productions. For the passive CMOS strip detectors project we fabricated strip detectors in a CMOS foundry using two 1 cm2 reticles that are stitched together along the wafer. The fabricated strips stitched the reticles three and five times, and it was shown that the performance of those strips is not affected by the stitching. This paper shows 3D TCAD simulations of the stitching area to investigate the possible effects stitching can have on the performance of the strip detectors, considering different stitching mismatches. We will show that the mismatch of stitched structures up to 1 um does not impact the performance with TCAD simulations which agrees with the results obtained from the measurements.