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arXiv · 2411.00309

From Flip FET to Flip 3D Integration (F3D): Maximizing the Scaling Potential of Wafer Both Sides Beyond Conventional 3D Integration

Heng Wu·Haoran Lu·Wanyue Peng·Ziqiao Xu·Yanbang Chu·Jiacheng Sun·Falong Zhou·Jack Wu·Lijie Zhang·Weihai Bu·Jin Kang·Ming Li·Yibo Lin·Runsheng Wang·Xin Zhang·Ru Huang
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Abstract

In this work, we proposed a new 3D integration technology: the Flip 3D integration (F3D), consisting of the 3D transistor stacking, the 3D dual-sided interconnects, the 3D die-to-die stacking and the dual-sided Monolithic 3D (M3D). Based on a 32-bit FFET RISCV core, besides the scaling benefits of the Flip FET (FFET), the dual-sided signal routing shows even more routing flexibility with 6.8% area reduction and 5.9% EDP improvement. Novel concepts of Multi-Flipping processes (Double Flips and Triple Flips) were proposed to relax the thermal budget constraints in the F3D and thus support the dual-sided M3D in the F3D. The core's EDP and frequency are improved by up to 3.2% and 2.3% respectively, after BEOL optimizations based on the Triple Flips compared with unoptimized ones.

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Heng Wu, Haoran Lu, Wanyue Peng, Ziqiao Xu, Yanbang Chu, Jiacheng Sun, Falong Zhou, Jack Wu, Lijie Zhang, Weihai Bu, Jin Kang, Ming Li, Yibo Lin, Runsheng Wang, Xin Zhang, Ru Huang. 2024-11-01. From Flip FET to Flip 3D Integration (F3D): Maximizing the Scaling Potential of Wafer Both Sides Beyond Conventional 3D Integration. https://arxiv.org/abs/2411.00309

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